- 12 2月, 2020 4 次提交
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由 yiicy 提交于
[OPENCL] add sigmoid image2d kernel and ut
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由 zhupengyang 提交于
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由 zhupengyang 提交于
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由 xiaogang 提交于
* fix: update fpga backend and kernel test=develop * style: style fix test=develop
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- 11 2月, 2020 3 次提交
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由 Yiqun Liu 提交于
* Optimize the transform from Paddle' Tensor to EigenVector, avoiding defining multiple DDim. * Optimize the compute implementation of several operators. test=develop
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由 Yiqun Liu 提交于
* Optimize the InferShape of several operators. test=develop * Remove the new function, resize and CheckPositive in DDim. test=develop * Fix a bug in fc_op's InferShape. test=develop
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由 huzhiqiang 提交于
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- 10 2月, 2020 4 次提交
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由 xiaogang 提交于
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由 Yuan Shuai 提交于
[LITE][OPENCL] Add 3 kernels of ElementwiseAdd/FusionElemenwiseAddAct op with opencl image format (#2844) * [LITE][OPENCL] Add 3 kernels of ElementwiseAdd/FuseElementwiseAdd op. test=develop
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由 huzhiqiang 提交于
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由 hong19860320 提交于
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- 08 2月, 2020 2 次提交
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由 Yiqun Liu 提交于
test=develop
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由 xiebaiyuan 提交于
* [LITE][OPENCL][Image]develop 1x1/5x5/7x7 routing in conv_compute ,test=develop * [LITE][OPENCL][Image]develop 1x1/5x5/7x7 routing in conv_compute ,convert bias filter in prepare for run ,test=develop
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- 07 2月, 2020 2 次提交
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由 Yuan Shuai 提交于
* [LITE][OPENCL] remove useless code. test=develop * [LITE][OPENCL] finish 4 kernel and unit tests of image2d opencl elementwise_mul kernel. test=develop * [LITE][OPENCL] Fix little bug of ASSERT. test=develop * [LITE][OPENCL] Fix bug of channel_mul_d2 and d4. test=develop
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由 liu zhengxi 提交于
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- 06 2月, 2020 2 次提交
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由 huzhiqiang 提交于
* FIX CXX DEMO MAKEFILE TO SUPPORT MAC COMPILE test=develop * test=develop
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由 juncaipeng 提交于
* optimize quant_dequant_fuse_pass, test=develop * update, test=develop * update, test=develop * fix bug for accessing the removed node, test=develop * set the bias of int8 conv as float, test=develop * support weight quantization, test=develop * up, test=develop * up, test=develop * up, test=develop
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- 05 2月, 2020 1 次提交
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由 HappyAngel 提交于
[arm] fix conv_dw leakyRelu compute error
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- 04 2月, 2020 2 次提交
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由 yiicy 提交于
* refactor 5x5s1 dw conv armv8, test=develop * [ARM] refactor depthwise conv 5x5s1, and support relu6, leakey relu, test=develop * [ARM] sgemv support fuse relu6 and leakey relu,test=develop * [ARM] reduce some conv ut case, test=develop * [ARM] fix 5x5dw conv pick kernel bug, test=develop * fix code style, test=develop * [ARM] fix sgemv fuse relu6 bug, test=develop * [ARM] fix fp32 5x5s1 dw bug, test=develop * [ARM] fix fp32 5x5 dw conv pick kernel bug, test=develop
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由 juncaipeng 提交于
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- 03 2月, 2020 3 次提交
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由 Yuan Shuai 提交于
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由 huzhiqiang 提交于
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由 xiebaiyuan 提交于
* [LITE][OPENCL]develop basic image depthwiseconv,passed loop test,test=develop * [LITE][OPENCL]log to vlog(4),test=develop * [LITE][OPENCL]fix depthwise buffer conv kernel name ,test=develop
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- 24 1月, 2020 1 次提交
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由 zhupengyang 提交于
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- 22 1月, 2020 1 次提交
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由 HappyAngel 提交于
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- 21 1月, 2020 1 次提交
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由 zhupengyang 提交于
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- 19 1月, 2020 5 次提交
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由 huzhiqiang 提交于
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由 Wilber 提交于
- modify aligned_matmul kernel for dynamically malloc memory - fix top_k_avg_pooling kernel to support data whose size is more than cuda shared memory.
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由 HappyAngel 提交于
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由 zhupengyang 提交于
* [NPU] reshape x,y,out node in elementwise ops
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由 xiebaiyuan 提交于
* [LITE][OPENCL] conv2d_1x1_image, choose simple kernel when in some case. for opencl ,test=develop * [LITE][OPENCL] conv2d_1x1_image, add looptest ,test=develop
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- 17 1月, 2020 2 次提交
- 16 1月, 2020 4 次提交
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由 huzhiqiang 提交于
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由 zhupengyang 提交于
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由 HappyAngel 提交于
1. add conv_5x5s2_dw to support any padding 2. add 1x1s2pooling impl 3. fix conv dw 3x3 s1p01 bug
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由 Wilber 提交于
test_model_bin support print intermediate tensor.
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- 15 1月, 2020 3 次提交
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由 HappyAngel 提交于
* fix, test=develop * add fc_relu, test=develop
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由 Wilber 提交于
- 修复var_conv_2d级联使用中计算错误的bug - x86的var_conv_2d中显示指定lod level为3
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由 hong19860320 提交于
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