conv_bn_relu_kernel.cpp

/* Copyright (c) 2018 PaddlePaddle Authors. All Rights Reserved.

Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License. */

#ifdef FUSION_CONVBNRELU_OP

#include "operators/kernel/conv_bn_relu_kernel.h"

namespace paddle_mobile {
namespace operators {

template <>
bool ConvBNReluKernel<FPGA, float>::Init(FusionConvBNReluParam<FPGA> *param) {
  bool relu_enabled = true;
  auto input = const_cast<Tensor *>(param->Input());
  auto input_ptr = input->data<float>();
  auto filter = const_cast<Tensor *>(param->Filter());
  auto out = param->Output();
  auto bn_mean_ptr = param->InputMean()->data<float>();
  auto bn_var_ptr = param->InputVariance()->data<float>();
  auto bn_scale_ptr = param->InputScale()->data<float>();
  auto bn_bias_ptr = param->InputBias()->data<float>();
  const float epsilon = param->Epsilon();
  PADDLE_MOBILE_ENFORCE(out->dims()[1] == param->InputBias()->dims()[0],
                        "Output channel should be equal to bias number");
  const int channel = out->dims()[1];
  auto bs_ptr = (float *)fpga::fpga_malloc(2 * channel * sizeof(float));
  auto new_scale = new Tensor();
  auto new_bias = new Tensor();
  auto new_scale_ptr = new_scale->mutable_data<float>({channel});
  auto new_bias_ptr = new_bias->mutable_data<float>({channel});

  for (int i = 0; i < channel; i++) {
    new_scale_ptr[i] = bn_scale_ptr[i] /
                       static_cast<float>(pow((bn_var_ptr[i] + epsilon), 0.5));
    new_bias_ptr[i] = bn_bias_ptr[i] + (0 - bn_mean_ptr[i]) * new_scale_ptr[i];
    bs_ptr[i + channel] = new_scale_ptr[i];
    bs_ptr[i] = new_bias_ptr[i];
  }
  param->SetNewScale(new_scale);
  param->SetNewBias(new_bias);

  float max_value = fpga::filter_find_max(filter);
  fpga::format_filter(filter, max_value, param->Groups());
  auto filter_ptr = filter->data<float>();

  int element_num_per_div =
      fpga::get_element_num_per_div(filter, param->Groups());
  fpga::format_bias_scale_array(&bs_ptr, element_num_per_div, channel);

  fpga::format_ofm(out);
  auto out_ptr = out->mutable_data<float>();

  fpga::WrapperConvArgs convArgs;
  convArgs.group_num = (uint32_t)param->Groups();
  convArgs.split_num = (uint32_t)fpga::get_plit_num(filter);
  convArgs.filter_num = (uint32_t)filter->dims()[0];
  convArgs.output.address = out_ptr;
  convArgs.output.scale_address = out->scale;
  convArgs.conv_args = (fpga::ConvArgs *)fpga::fpga_malloc(
      convArgs.split_num * sizeof(fpga::ConvArgs));
  param->SetFpgaArgs(convArgs);

  int element_num = fpga::get_aligned_filter_element_num(
      filter->dims()[1] * filter->dims()[2] * filter->dims()[3]);

  int n = convArgs.split_num;
  for (int i = 0; i < n; i++) {
    convArgs.conv_args[i].relu_enabled = relu_enabled;
    convArgs.conv_args[i].group_num = (uint32_t)param->Groups();
    convArgs.conv_args[i].kernel.stride_h = (uint32_t)param->Strides()[0];
    convArgs.conv_args[i].kernel.stride_w = (uint32_t)param->Strides()[1];
    convArgs.conv_args[i].kernel.height = (uint32_t)filter->dims()[2];
    convArgs.conv_args[i].kernel.width = (uint32_t)filter->dims()[3];
    convArgs.conv_args[i].image.address = input_ptr;
    convArgs.conv_args[i].image.channels = (uint32_t)input->dims()[1];
    convArgs.conv_args[i].image.height = (uint32_t)input->dims()[2];
    convArgs.conv_args[i].image.width = (uint32_t)input->dims()[3];
    convArgs.conv_args[i].image.pad_height = (uint32_t)param->Paddings()[0];
    convArgs.conv_args[i].image.pad_width = (uint32_t)param->Paddings()[1];
    convArgs.conv_args[i].filter_address =
        &((int8_t *)filter_ptr)[i * element_num];
    convArgs.conv_args[i].sb_address = &((int8_t *)bs_ptr)[i * element_num];
    convArgs.conv_args[i].filter_num =
        (uint32_t)(i == n - 1 ? fpga::get_aligned_filter_num(
                                    channel - (n - 1) * element_num_per_div)
                              : element_num_per_div);
    convArgs.conv_args[i].output.scale_address =
        (float *)fpga::fpga_malloc(2 * sizeof(float));
    convArgs.conv_args[i].image.scale_address = input->scale;
  }
  return true;
}

template <>
void ConvBNReluKernel<FPGA, float>::Compute(
    const FusionConvBNReluParam<FPGA> &param) const {
  fpga::ComputeFpgaConv(param.FpgaArgs());
}
template class ConvBNReluKernel<FPGA, float>;

}  // namespace operators
}  // namespace paddle_mobile

#endif