Tested on my Dalmore E1611 board, eMMC and SD-Card work fine, can load
a kernel off of an SD card OK, card detect works, and the env is now
stored in eMMC (end of the 2nd 'boot' sector, same as Tegra20/30).
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

T114 requires SD bus power-rail bringup for the SDIO card on SDMMC3.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

SDIO1 (the SD-card slot on Dalmore) needs to have its pads setup
before the MMC driver is added.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Took these values directly from the kernel dts files.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Turn on SPI in dalmore config file
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Add driver for tegra114 SPI controller.  This controller is not
compatible with either the tegra20 or tegra30 controllers, so it
requires a new driver.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Dalmore has a SPI flash part attached to controller 4, so enable
controller 4 and set to 25MHz.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Add nodes for t114 SPI controller hardware
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Add node for apbdma controller hardware.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Add "nvidia,tegra114-spi" to represent t114 SPI controller hardware.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Add support for Winbond W25Q32DW 32Mbit part
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Add a common interface to fdt based SPI drivers.  Each driver is
represented by a table entry in fdt_spi_drivers[].  If there are
multiple SPI drivers in the table, the first driver to return success
from spi_init() will be registered as the SPI driver.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Make the tegra20 SPI driver similar to the tegra30 (and soon to be
tegra114) SPI drivers in preparation of common fdt SPI driver front
end.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Move register structs from headers into .c files and use common name.
This is in preparation of making common fdt front end for SPI
drivers.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Remove non fdt support from tegra20 and tegra30 SPI drivers in
preparation of new common fdt based SPI driver front end.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Rename tegra SPI drivers to tegra20_flash and tegra20_slink in
preparation for commonization and addition of tegra114_spi.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

This feature was only used for tegra20 seaboard that had a pinmux
conflict on the SPI pins.  These boards were never manufactured, so
remove this support to clean up SPI driver.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Gets rid of warnings from omap_gpio:
ERROR : check_gpio: invalid GPIO -1

(and undefined behaviour as the -1 error code is interpreted as gpio value)
Signed-off-by: NPeter Korsgaard <peter.korsgaard@barco.com>

Let mmc_getcd() return true and mmc_getwp() false if mmc driver doesn't
provide handlers for them.
Signed-off-by: NPeter Korsgaard <peter.korsgaard@barco.com>
[trini: Add braces around first if test in each case to fix warning]
Signed-off-by: NTom Rini <trini@ti.com>

All of these platforms have memory starting at 0x80000000, so this is
the correct CONFIG_STANDALONE_LOAD_ADDR for all of them.
Acked-by: NPeter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: NTom Rini <trini@ti.com>

Tested-by: NRao Bodapati <rao@circuitco.com>
Signed-off-by: NTom Rini <trini@ti.com>

Add TI814X EVM board directory, config file, and MAINTAINERS
entry. Enable build.
Signed-off-by: NMatt Porter <mporter@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>
[trini: Adapt to recent omap_hsmmc requirements, Matt re-tested]
Signed-off-by: NTom Rini <trini@ti.com>

TI814X requires the same quirks as AM33XX to be enabled.
Signed-off-by: NMatt Porter <mporter@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

TI814x has a 192MHz hsmmc reference clock. Select that clock rate
when building for TI814x.
Signed-off-by: NMatt Porter <mporter@ti.com>

Adds a config_dmm() routine to support TI814X DMM configuration.
Signed-off-by: NMatt Porter <mporter@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

Support the ti814x specific register definitions within
arch-am33xx.
Signed-off-by: NMatt Porter <mporter@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

AM33XX and TI814X have a similar mux though the pinmux register
layout and address space differ. Add a separate ti814x mux include
to support the TI814X-specific differences.
Signed-off-by: NMatt Porter <mporter@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>
Acked-by: NPeter Korsgaard <jacmet@sunsite.dk>

Split clock.c for am335x and ti814x and add ti814x specific
clock support.
Signed-off-by: NMatt Porter <mporter@ti.com>

The AM33xx emif4/ddr support closely matches what is need to support
TI814x except that TI814x has two EMIF instances. Refactor all the
emif4 helper calls and the config_ddr() init function to use an
additional instance number argument.
Signed-off-by: NMatt Porter <mporter@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

Eliminate AM33xx specific names to prepare for TI814x support
within AM33xx-land.
Signed-off-by: NMatt Porter <mporter@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

- In arch/arm/cpu/armv7/omap-common/timer.c,
  drivers/mtd/nand/omap_gpmc.c and drivers/net/cpsw.c add #include files
  that the driver needs but had been relying on <config.h> to bring in.
- In arch/arm/cpu/armv7/omap-common/lowlevel_init.S add <config.h>
- In am335x_evm.h and pcm051.h don't globally include
  <asm/arch/hardware.h> and <asm/arch/cpu.h> but just <asm/arch/omap.h>
  as that is the only include which defines things the config uses.

Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: NTom Rini <trini@ti.com>

With v3.9 and later of the Linux Kernel defaulting to multi-platform
images with omap2plus_defconfig, uImage isn't builtable anymore by
default.  Add CONFIG_CMD_BOOTZ so that we can still boot something the
kernel spits out.
Signed-off-by: NEnric Balletbo i Serra <eballetbo@iseebcn.com>
Reviewed-by: NJavier Martinez Canillas <javier@dowhile0.org>

Just fix a typo displaying the CPU info. With CONFIG_DISPLAY_INFO we see
something like AMAM335X-GP rev 0 instead of AM335X-GP rev 0.
Signed-off-by: NEnric Balletbo i Serra <eballetbo@iseebcn.com>
Reviewed-by: NJavier Martinez Canillas <javier@dowhile0.org>

Enable DDR PHY dynamic power down bit, which enables
powering down the IO receiver when not performing read.

This also helps in reducing overall power consumption in
low power states (suspend/standby).
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: NSatyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
Cc: Tom Rini <trini@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

Tegra20 requires the workaround for this erratum. Enable it.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add common code to enable the workaround for ARM erratum 716044. This
will be enabled for Tegra.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The original write to sdram_config is correct for DDR3 but incorrect
for DDR2 so SPL was hanging. For DDR2, the write to sdram_config
should be after the writes to ref_ctrl. This was working for DDR3
because there was a write of 0x2800 to ref_ctrl before a write
to sdram_config.

Tested on: GP EVM 1.1A (DDR2), GP EVM 1.5A (DDR3),
           Beaglebone A6 (DDR2), Beagleone Blacd A4A (DDR3)
Signed-off-by: NSteve Kipisz <s-kipisz2@ti.com>

Make bootcmd run findfdt so that we know what dtb file to load.  Add a
loadfdt command to load this file in.  Make mmcboot pass in ${fdtaddr}
and make the mmc section of bootcmd run loadfdt.
Signed-off-by: NKoen Kooi <koen@dominion.thruhere.net>
Signed-off-by: NTom Rini <trini@ti.com>
Acked-by: NPeter Korsgaard <jacmet@sunsite.dk>

The kernel is loaded from some form of ext[234] or FAT, depending on the
distribution used.  We add a bootpart variable to the environment so
that we can load from the correct mmc partition as well.  We leave
CONFIG_CMD_EXT2 for existing scripts that use ext2load.
Signed-off-by: NKoen Kooi <koen@dominion.thruhere.net>
Signed-off-by: NTom Rini <trini@ti.com>
Acked-by: NPeter Korsgaard <jacmet@sunsite.dk>