Add a default implementation of this method which always indicates that
the last reset was a power-on reset. This is the most likely type of reset
and without a PCH-specific driver we cannot determine any other type.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

On modern x86 devices we can power the system off using the power-
management features of the PCH. Add an implementation for this.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

The EFI implementation of reset sits inside the driver and is called
directly from outside the driver, breaking the normal driver-model
conventions. Worse, it passed NULL as the device pointer, hoping that
the called function won't use it, which breaks as soon as code is added
to use it.

Separate out the implementation to improve the situation enough to allow
a future patch to add new sysreset features.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Implement this ioctl() to support power off.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Implement this ioctl() to support power off.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add a new ioctl() request to read information about the power-management
system. This can be used to power off the device.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

When the MRC cache fails to save it is useful to have some debugging info
to indicate what when wrong. Add some more debug() calls.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

When SPL is used to set up the memory controller we want to save the MRC
data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a
function to handle that.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds
and identifies the CPU.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Allow broadwell to build for SPL and include the reference code.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

At present broadwell only supports booting straight into U-Boot proper.
Add a separate init file to boot from SPL into U-Boot proper, and select
it when SPL is in use.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

At present we support having 16-bit init be in SPL or U-Boot proper, but
not TPL. Add support for this so that TPL can boot.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

When a previous phase of U-Boot has run we need to adjust the init of
subsequent states to avoid messing up the CPU state.

Add a new version of the start logic for SPL, when it boots from TPL
(start_from tpl.c) and a new version for U-Boot when it boots from SPL.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Split the CPU init into two parts - the 'full' init which happens in the
first U-Boot phase, and the rest of the init that happens on subsequent
stages.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

At present the debug UART is set up in sdram.c which is not the best place
since it has nothing in particular to do with SDRAM. Since we want to
support initing this in SPL too, move it to a common file.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
[bmeng: added 'broadwell' tag in the commit title]
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>

At present, for broadwell, SDRAM is always set up in U-Boot proper since
the 64-bit mode (which uses SDRAM init in SPL) is not supported.

Update the code to allow SDRAM init in SPL instead so that U-Boot proper
can be loaded into SDRAM and run from there. This allows U-Boot to be
compressed to reduce space, since it is not necessary to run it directly
from flash. It could later allow us to support 64-bit U-Boot on broadwell.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add debugging during SDRAM init so that problems are easier to
diagnose.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add an arch-specific handoff header so that we can use the HANDOFF feature
on x86 devices.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Some boards want to use TPL as the first phase of U-Boot. This allows
selection of A or B SPL phases, thus allowing the memory init to be
upgraded in the field.

Add a new Kconfig option for this.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

At present only chromebook_link64 supports SPL. It is useful to eb able to
support both TPL and SPL to implement verified boot on x86.

Enable the options for both along with some suitable default options
needed to boot through these phases.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add labels for these nodes so that board DT files can reference them.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

We cannot init the CPU fully both than once during a boot. Add a new
function which can be called to figure out the CPU identity, but which
does not change anything. For x86_64, this is empty for now.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

At present many of the functions in this file return -1 as an error
number. which is -EPERM. Update the code to use real error numbers.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

We use binman to build the x86 image now. Update a comment which still
refers to ifdtool.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

There is a typo in this header. Fix it.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This reverts commit aec4298c.

Unfortunately this has a dramatic impact on the pre-relocation memory
used on x86 platforms (increasing it by 2KB) since it increases the
overhead for each PCI device from 220 bytes to 412 bytes.

The offending line is in UCLASS_DRIVER(pci):

	.per_device_auto_alloc_size = sizeof(struct pci_controller),

This means that all PCI devices have the controller struct associated
with them. The solution is to move the regions[] member out of the array,
makes its size dynamic, or split UCLASS_PCI into controllers and
non-controllers, as the comment suggests.

For now, revert the commit to get things running again.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Device-tree rules require that aliases use a hyphen rather than a
underscore. Update the uclass name to fit with this.

This allows device-tree aliases to be used to refer to cros-ec devices,
for example:

	aliases {
	    cros-ec0 = &ec;
	    cros-ec1 = &pd;
	};
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

At present only OF_SEPARATE is considered valid for building a device-tree
file in SPL. However sandbox uses OF_HOSTFILE instead. Update the logic to
handle this and make it easier to understand.

Note that the new logic is not quite the same as the old logic. It was
previously assumed that checking for:

   $(CONFIG_$(SPL_TPL_)OF_CONTROL)
   $(CONFIG_OF_SEPARATE)
   $(CONFIG_$(SPL_TPL_)OF_PLATDATA)

producing 'yy' meant that the first two were 'y' and the last was empty.
Strictly speaking it would be possible for any two of the three to be 'y'
and still yield the same result. However, that was not the intention of
the new logic, since OF_PLATDATA always ensures that no device-tree file
is included. So in effect the new logic is the same, with the addition of
OF_HOSTFILE as an option for OP_SEPARATE.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Update the condition to translate only if this is enabled for SPL.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

At present sections are always placed automatically. Even if an 'offset'
property is provided it is ignored. Update the logic to support an offset
for sections.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

An important property is missing. Update the entry comment to include
this.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This message is not very important since it is simply indicating that the
user's instructions are being followed. Only show it when the verbosity
level is above the default.

Also drop the unnecessary extra newline on this message, which causes two
line breaks.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

It is not good practice to raise an exception in a constructor. In this
case the 'text' entry may not actually be used, if -i is used to filter
out the images that get built.

Move the exception to where the data is actually used.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

- RZ/A1 addition.
- Old board removal.

- Assorted stratix10 fixes.
- DDR driver DM migration.

Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach,
which is a cheap development platform with RZ/A1H SoC. The
DTs are imported from Linux 5.0.11, commit d5a2675b207d .

Currently supported are UART, ethernet and RPC SPI. The board
can be booted from RPC SPI by writing the u-boot.bin binary
to the beginning of the SPI NOR, e.g. using the "sf" command.
The board can also be booted via JTAG by setting text base to
0x20020000, loading u-boot.bin there via JTAG and executing it
from that address.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC.
Distinguishing feature of this SoC is that it has up to
10 MiB of on-SoC static RAM (SRAM).

The DTs are imported from Linux 5.0.11, commit d5a2675b207d .
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Add ifdeffery to allow operation without the clock framework
enabled. This is required on RZ/A1, as it does not have clock
driver yet.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Add ifdeffery to allow operation without the clock framework
enabled. This is required on RZ/A1, as it does not have clock
driver yet.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Add support for RZ/A1 SoC specifics.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>