We can enable / disable trace feature from the FTRACE config options.
To enable, compile U-Boot with FTRACE=1.

This patch add #ifdef FTRACE in exynos5-common.h for enable/disable
to use FTRACE configs instead of having to change board config files.
Signed-off-by: NInha Song <ideal.song@samsung.com>
Acked-by: NSimon Glass <sjg@chroimum.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Commit 2e82e925 'Exynos: Clock: Cleanup
soc_get_periph_rate' introduced a bug in I2C config. This patch makes cros_ec
keyboard working again on Samsung Chromebook (snow).

Changes in V2: reorder lines as requested by Joonyoung Shim.
Signed-off-by: NGuillaume GARDET <guillaume.gardet@free.fr>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Joonyoung Shim <jy0922.shim@samsung.com>
Reviewed-by: NSimon Glass <sjg@chroimum.org>
Tested-by: NSimon Glass <sjg@chroimum.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Conflicts:
	board/armltd/vexpress64/vexpress64.c
Signed-off-by: NTom Rini <trini@konsulko.com>

With the most recent board firmware correct SDIO clock is 50MHz as
opposed to 25 MHz before.

Also set max frequency of MMC data exchange equal to SDIO clock -
because there's no way to transfer data faster than interface clock.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache).
This change adds functions required for controlling SLC:
 * slc_enable/disable
 * slc_flush/invalidate

For now we just disable SLC to escape DMA coherency issues until either:
 * SLC flush/invalidate is supported in DMA APIin U-Boot
 * hardware DMA coherency is implemented (that might be board specific
   so probably we'll need to have a separate Kconfig option for
   controlling SLC explicitly)
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>

Now when all infrastructure in ARC is ready for it let's switch ARC UART
to driver model.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>

 [1] Fix misspeling in ARC_CACHE_LINE_SHIFT dependency, now cache-line
lenth selection is correctly enabled if either I$ or D$ are enabled.

 [2] Add dummy entry to target list to make sure target type is always
mentioned in defconfig. Otherwise defconfig for the first target in the
list will not have target name and later on with addition of the new
target on top of the list in Kconfig will lead to corrupted
configuration expanded from defconfig.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

As discussed on mailing list we're drifting away from
CONFIG_SYS_GENERIC_GLOBAL_DATA in favour to use of board_init_f_mem()
for global data.

So do this for ARC architecture.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Before that moment our defconfigs were manually modified with addition
of new options. That means once anybody wants to add another option and
re-genarate defconfig with "make defconfig" there will be lots of
differences. So to make future modifications more clean we'll do bulk
re-generation right away.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Intention behind this work was elimination of as much assembly-written
code as it is possible.

In case of ARC we already have relocation fix-up implemented in C so why
don't we use C for U-Boot copying, .bss zeroing etc.

It turned out x86 uses pretty similar approach so we re-used parts of
code in "board_f.c" initially implemented for x86.

Now assembly usage during init is limited to stack- and frame-pointer
setup before and after relocation.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>

This separation makes maintenance of code easier because those low-level
interrupt- or exception handling routines are pretty static and usually
require not much care while start-up code is a subject of modifications
and enhancements.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Even though ARCompact and ARCv2 are not binary compatible most of
assembly instructions are used in both. With this change we'll get rid
of duplicate code.

Still IVTs are implemented differently so we're keeping them in separate
files.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

always

Make both invalidate_icache_all() and invalidate_dcache_all() available
even if U-Boot is configured with CONFIG_SYS_DCACHE_OFF and/or
CONFIG_SYS_ICACHE_OFF.

This is useful because configuration of U-Boot may not match actual
hardware features. Real board may have cache(s) but for some reason we
may want to run U-Boot with cache(s) disabled (for example if some
peripherals work improperly with existing drivers if data cache is
enabled). So board may start with cache(s) enabled (that's the case for
ARC cores with built-in caches) but early in U-Boot we disable cache(s)
and make sure all contents of data cache gets flushed in RAM.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Being global variable with 0 value it falls into .bss area which we may
only use after relocation to RAM. And right afetr relocation we zero
.bss - effectively cleaing register address set for early console.

Now with pre-set value "regs" variable is no longer in .bss and this way
safely survives relocation.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

Create a new configuration file: at91-sama5_common.h. Which includes the
configurations that reused by all SAMA5 chips.

at91-sama5_common.h includes:
- hw macros (clock, text_base and etc.)
- default commands.
- BOOTARGS
- U-Boot common configs.
NOTE: NOR flash definition should be put before including the common header.

For sama5d3-xplained:
- add CMD_SETEXPR

For sama5d3xek:
- add CMD_SETEXPR
- change CONFIG_SYS_MALLOC_LEN to (4*1024*1024)
Signed-off-by: NJosh Wu <josh.wu@atmel.com>

Enable SPL support for at91sam9n12ek boards, now it supports
boot up from NAND flash, serial flash.
Signed-off-by: NBo Shen <voice.shen@atmel.com>

Enable SPL support for at91sam9x5ek board. Now, it supports
boot up from NAND flash and SPI flash.
Signed-off-by: NBo Shen <voice.shen@atmel.com>

Supports boot up from NAND flash with software ECC eanbled.
And supports boot up from SD/MMC card with FAT file system.

As the boot from SD/MMC card with FAT file system, the BSS
segment is too big to fit into SRAM, so, use the lds to put
it into SDRAM.
Signed-off-by: NBo Shen <voice.shen@atmel.com>

Config MCKR according to the datasheet sequence, or else it
will cause the MCKR configuration failed.

Remove timeout checking for clock configuration, if configure
the clock failed, let the system hang while not run in wrong
clock configuration.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Tested-by: NHeiko Schocher <hs@denx.de>

Insteading in mmc's raw sectors, this patch will save the environment
in a fat file (uboot.env) in mmc card's first FAT patition by default.

If you want to save in mmc's raw sectors, you only need to define
CONFIG_ENV_IS_IN_MMC.
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Acked-by: NBo Shen <voice.shen@atmel.com>

Add support for on-flash bad block table. This makes U-Boot handle an existing
BBT correctly.
Signed-off-by: NDavid Dueck <davidcdueck@googlemail.com>
Reviewed-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
CC: Boris BREZILLON <boris.brezillon@free-electrons.com>
CC: Josh Wu <josh.wu@atmel.com>
CC: Andreas Bießmann <andreas.devel@googlemail.com>
CC: Scott Wood <scottwood@freescale.com>
Acked-by: NJosh Wu <josh.wu@atmel.com>

move MACH_TYPE into defconfig
Signed-off-by: NHeiko Schocher <hs@denx.de>

To facilitate changing lowlevel_init to become s_init, move the current
contents of s_init into board_init_f and add the rest of what
board_init_f does here.
In order to compile clean without CONFIG_SKIP_LOWLEVEL_INIT set, leave an
empty stub of s_init(). It can be removed when lowlevel_init becomes s_init.

Cc: Bo Shen <voice.shen@atmel.com>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Matt Porter <mporter@konsulko.com> on sama5d3_xplained
Signed-off-by: NTom Rini <trini@ti.com>
[rebased on current master, leave s_init() as empty stub]
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

The commit 8dfafdde (Introduce common timer functions), add common
timer functions, we can use them directly.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
[rebase on current master]
Sigend-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Signed-off-by: NBo Shen <voice.shen@atmel.com>
[rebase on current master]
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

This patch will display the U-Boot version on LCD.
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Acked-by: NBo Shen <voice.shen@atmel.com>

Testing showed, that commands like STATUS made the buffer dirty
when executed with NFC_SECSZ set to the page size. It looks
like the controller transfers bogus data when this register
is configured. When setting it to 0, the buffer does not get
altered while the status command still seems to work flawless.
Signed-off-by: NStefan Agner <stefan@agner.ch>

The driver tries to re-use the page buffer by storing the page
number of the current page in the buffer. The page is only read
if the requested page number is not currently in the buffer. When
a block is erased, the page number is marked as invalid if the
erased page equals the one currently in the cache. However, since
a erase block consists of multiple pages, also other page numbers
could be affected.

The commands to reproduce this issue (on a written page):
> nand dump 0x800
> nand erase 0x0 0x20000
> nand dump 0x800

The second nand dump command returns the data from the buffer,
while in fact the page is erased (0xff).

Avoid the hassle to calculate whether the page is affected or not,
but set the page buffer unconditionally to invalid instead.
Signed-off-by: NStefan Agner <stefan@agner.ch>

This command is only enabled by one board, complicates the NAND code,
and doesn't appear to have been functioning properly for several
years.  If there are no bad blocks in the NAND region being written
nand_write_skip_bad() will take the shortcut of calling nand_write()
which bypasses the special yaffs handling.  This causes invalid YAFFS
data to be written. See
http://lists.denx.de/pipermail/u-boot/2011-September/102830.html for
an example and a potential workaround.

U-Boot still retains the ability to mount and access YAFFS partitions
via CONFIG_YAFFS2.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

The CONFIG_MTD_NAND_VERIFY_WRITE has been removed from Linux for some
time and a more generic method of NAND verification now exists in U-Boot.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Tested-by: NHeiko Schocher <hs@denx.de>
Acked-by: NHeiko Schocher <hs@denx.de>

Previously NAND writes were not verified and could fail silently.  Add
a verification step after all writes to NAND.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Reviewed-by: NLukasz Majewski <l.majewski@samsung.com>
Tested-by: NHeiko Schocher <hs@denx.de>
Acked-by: NHeiko Schocher <hs@denx.de>

Previously NAND writes were only verified when CONFIG_MTD_NAND_VERIFY_WRITE
was defined.  On boards without this define writes could fail silently.
Boards with CONFIG_MTD_NAND_VERIFY_WRITE could prematurely report
failures which ECC could correct.

Add a verification step after all "nand write[.x]" commands to ensure the
writes were successful.  The verification uses ECC for for "normal"
writes, but does not for raw and yaffs writes.  Some test cases which
inject fake bad bits on a 2K page flash are below.

Test cases with CONFIG_MTD_NAND_VERIFY_WRITE defined:
  Example of an ECC write which previously failed when
  CONFIG_MTD_NAND_VERIFY_WRITE was defined, but now succeeds because ECC
  is used during verification:
      nand erase 0 0x10000
      dhcp /somefile
      mw.b 0x10000 0xff 0x2000
      mw.b 0x10020 0xfe 1
      nand write.raw 0x10000 0x800 1
      mw.b 0x1000020 0x01 1
      nand write 0x1000000 0x800 0x1800

Test cases without CONFIG_MTD_NAND_VERIFY_WRITE defined:
  Example of an ECC write which previously silently failed:
      nand erase 0 0x10000
      dhcp /somefile
      mw.b 0x10000 0xff 0x2000
      mw.b 0x10020 0x00 1
      nand write.raw 0x10000 0x800 1
      mw.b 0x1000020 0xff 1
      nand write 0x1000000 0x800 0x1800

  Example of a raw write which previously failed silently due to stuck
  data bit, but now errors out:
      nand erase 0 0x10000
      dhcp /somefile
      mw.b 0x10000 0xff 0x2000
      mw.b 0x10020 0xfe 1
      nand write.raw 0x10000 0x800 1
      mw.b 0x1000020 0x01 1
      nand write.raw 0x1000000 0x800 3

  Example of a raw write which previously failed silently due to stuck OOB
  bit, but now errors out:
      nand erase 0 0x10000
      dhcp /somefile
      mw.b 0x10000 0xff 0x2000
      mw.b 0x10810 0xfe 1
      nand write.raw 0x10000 0x800 1
      mw.b 0x1000810 0x01 1
      nand write.raw 0x1000000 0x800 3
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Tested-by: NHeiko Schocher <hs@denx.de>
Acked-by: NHeiko Schocher <hs@denx.de>

Add nand_verify() and nand_verify_page_oob().  nand_verify() verifies
NAND contents against an arbitrarily sized buffer using ECC while
nand_verify_page_oob() verifies a NAND page's contents and OOB.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Tested-by: NHeiko Schocher <hs@denx.de>
Acked-by: NHeiko Schocher <hs@denx.de>

The use of the nand_write_options and nand_read_options structures were
removed in commit dfbf617f.  Remove the
now-unused structures too.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>