Init peripheral access control register of AIPSTZ OPACRx:

Buffer Writes(BW):      0 -> not bufferable,
Supervisor Protect(SP): 0 -> not require supervisor privilege level for accesses.
Write Protect(WP):      0 -> allows write accesses.
Trusted Protect(TP):    0 -> allows unstrusted master
Signed-off-by: NJason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>

There are 2 locations in the power init code for the mx28 where IRQs are not being cleared because incorrect methods to clear those bits were being used.  This was causing my board to get stuck waiting for POWER_CTRL_VDD5V_DROOP_IRQ to clear.  Using the correct method to clear the IRQs fixes it.
Signed-off-by: NZach Sadecki <zach@itwatchdogs.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>

Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

Remove 'all' target from Makefile, as this is unused code.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>

Use GENERATED_GBL_DATA_SIZE for calculating CONFIG_SYS_INIT_SP_OFFSET.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Remove 'all' target from Makefile, as this is unused code.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>

Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

For the i.mx6q, the burned-in MAC address will be the following odering,

fuse: 0x620[7:0]   MAC_ADDR[7:0]     ---> mac[5]
fuse: 0x620[15:8]  MAC_ADDR[15:8]    ---> mac[4]
fuse: 0x620[23:16] MAC_ADDR[23:16]   ---> mac[3]
fuse: 0x620[31:24] MAC_ADDR[31:24]   ---> mac[2]
fuse: 0x630[7:0]   MAC_ADDR[39:32]   ---> mac[1]
fuse: 0x630[15:8]  MAC_ADDR[47:40]   ---> mac[0]

This patch also fix the error caculation for the fuse bank[0] address
Signed-off-by: NJason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>

Add initial support for Freescale MX28EVK board.

Tested boot via SD card and by loading a kernel via TFTP through
the FEC interface.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Acked-by: NStefano Babic <sbabic@denx.de>

Let dram_init function be a common function, so that other mx28 boards
can reuse it.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>

Let imx_get_mac_from_fuse function be a common function, so that other
mx28 boards can reuse it.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Acked-by: NStefano Babic <sbabic@denx.de>

Add multi-FEC support for imx_get_mac_from_fuse by passing dev_id as a parameter.

This feature is important on mx28 SoC for example that has two FEC ports.

Cc: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NStefano Babic <sbabic@denx.de>

Bits 0 and 1 of CCM_CCGR7 are the usboh3 clock enable bits. Enabling this
clock is necessary for the USB download.
Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
CC: Jason Hui <jason.hui@linaro.org>
Acked-by: NJason Hui <jason.hui@linaro.org>

Config options for OMAP are not used with i.MX28 so remove dead code.
Signed-off-by: NVeli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NStefano Babic <sbabic@denx.de>

This enable the network function on the i.mx6q armadillo2
board(arm2), thus we can use tftp to load image from network.

Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: NJason Liu <jason.hui@linaro.org>
Tested-by: NDirk Behme <dirk.behme@de.bosch.com>

Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: NJason Liu <jason.hui@linaro.org>
Acked-by: NStefano Babic <sbabic@denx.de>

Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: NJason Liu <jason.hui@linaro.org>
Acked-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NStefan Kristiansson <stefan.kristiansson@saunalahti.fi>

Signed-off-by: NStefan Kristiansson <stefan.kristiansson@saunalahti.fi>

Signed-off-by: NStefan Kristiansson <stefan.kristiansson@saunalahti.fi>

Signed-off-by: NStefan Kristiansson <stefan.kristiansson@saunalahti.fi>

Signed-off-by: NStefan Kristiansson <stefan.kristiansson@saunalahti.fi>

Signed-off-by: NStefan Kristiansson <stefan.kristiansson@saunalahti.fi>

Signed-off-by: NStefan Kristiansson <stefan.kristiansson@saunalahti.fi>

Signed-off-by: NStefan Kristiansson <stefan.kristiansson@saunalahti.fi>

Signed-off-by: NStefan Kristiansson <stefan.kristiansson@saunalahti.fi>

Signed-off-by: NDavid Wagner <david.wagner@free-electrons.com>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

* 'master' of /home/wd/git/u-boot/custodians:
  fsl_lbc: add printout of LCRR and LBCR to local bus regs
  sbc8548: Fix up local bus init to be frequency aware
  sbc8548: enable support for hardware SPD errata workaround
  sbc8548: relocate fixed ddr init code to ddr.c file
  sbc8548: Make enabling SPD RAM configuration work
  sbc8548: Fix LBC SDRAM initialization settings
  sbc8548: enable ability to boot from alternate flash
  sbc8548: relocate 64MB user flash to sane boundary
  Revert "SBC8548: fix address mask to allow 64M flash"
  MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
  eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM
  eXMeritus HWW-1U-1A: Minor environment variable tweaks

* 'master' of git://git.denx.de/u-boot-mpc85xx:
  fsl_lbc: add printout of LCRR and LBCR to local bus regs
  sbc8548: Fix up local bus init to be frequency aware
  sbc8548: enable support for hardware SPD errata workaround
  sbc8548: relocate fixed ddr init code to ddr.c file
  sbc8548: Make enabling SPD RAM configuration work
  sbc8548: Fix LBC SDRAM initialization settings
  sbc8548: enable ability to boot from alternate flash
  sbc8548: relocate 64MB user flash to sane boundary
  Revert "SBC8548: fix address mask to allow 64M flash"
  MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
  eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM
  eXMeritus HWW-1U-1A: Minor environment variable tweaks

* 'master' of /home/wd/git/u-boot/custodians:
  fix: error ATMEL_FIO_BASE undeclared, if use I2C_Soft on AT91

* 'master' of git://git.denx.de/u-boot-i2c:
  fix: error ATMEL_FIO_BASE undeclared, if use I2C_Soft on AT91

* 'master' of /home/wd/git/u-boot/custodians:
  board/mpl/pati: use the CFI driver for the PATI board
  board/mpl/mip405: use the CFI driver for the MIP405/MIP405T board
  board/mpl/pip405: use the CFI driver for the PIP405 board
  board/mpl/common: remove the old legacy flash
  ppc4xx: Setup HICB on Io64

* 'master' of git://git.denx.de/u-boot-ppc4xx:
  board/mpl/pati: use the CFI driver for the PATI board
  board/mpl/mip405: use the CFI driver for the MIP405/MIP405T board
  board/mpl/pip405: use the CFI driver for the PIP405 board
  board/mpl/common: remove the old legacy flash
  ppc4xx: Setup HICB on Io64

* 'master' of /home/wd/git/u-boot/custodians:
  mpc8313erdb: fix mtdparts address
  powerpc/83xx/km: add support for 8321 based tuge1 board
  powerpc/83xx/km: merge tuxa and tuda1 boards to tuxx1
  powerpc/83xx/km: remove obsolete defines for tuda1
  powerpc/83xx/km: update SDRAM parameters for km8321 boards
  mpc8313erdb: Enable GPIO support on the MPC8313E RDB
  mpc83xx: Add a GPIO driver for the MPC83XX family
  gpio: Replace ARM gpio.h with the common API in include/asm-generic
  gpio: Modify common gpio.h to more closely match Linux

* 'master' of git://git.denx.de/u-boot-mpc83xx:
  mpc8313erdb: fix mtdparts address
  powerpc/83xx/km: add support for 8321 based tuge1 board
  powerpc/83xx/km: merge tuxa and tuda1 boards to tuxx1
  powerpc/83xx/km: remove obsolete defines for tuda1
  powerpc/83xx/km: update SDRAM parameters for km8321 boards
  mpc8313erdb: Enable GPIO support on the MPC8313E RDB
  mpc83xx: Add a GPIO driver for the MPC83XX family
  gpio: Replace ARM gpio.h with the common API in include/asm-generic
  gpio: Modify common gpio.h to more closely match Linux

* 'master' of /home/wd/git/u-boot/custodians:
  fsl_esdhc: fix PIO mode transfers
  mmc: tegra2: Implement card-detect hook.
  mmc: fsl_esdhc: Implement card-detect hook.
  mmc: Implement card detection.
  mmc: Change board_mmc_getcd() function prototype.
  drivers/mmc/mv_sdhci.c: Fix build warning
  ftsdc010: improve performance and capability
  mmc: add host_caps checking avoid switch card improperly
  i.mx: fsl_esdhc: add the i.mx6q support

It can be handy to have these in the output when trying to
debug odd behaviour.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The code here was copied from the mpc8548cds support, and it
wasn't using the CONFIG_SYS_LBC_LCRR define, and was just
unconditionally setting the LCRR_EADC bit.  Snooping with a
hardware debugger also showed we had LCRR_DBYP set, since we were
setting it based on a read of an uninitialized lcrr read via
clkdiv.  Borrow from the code in the tqm85xx.c support to add
LBC frequency aware masking of these bits.

This change will correct reliability issues associated with trying
to use the 128MB of LBC 100MHz SDRAM on this board.  Thanks to
Keith Savage for assistance in diagnosing the root cause of this.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Existing boards by default have an issue where the LBC SDRAM
SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51.

After the hardware modification listed in the README is made,
then the DDR2 SPD EEPROM appears at 0x53.  So this implements
a board specific get_spd() by taking advantage of the existing
weak linkage, that 1st tries reading at 0x53 and then if that
fails, it falls back to the old 0x51.

Since the old dependency issue of "SPD implies no LBC SDRAM"
gets removed with the hardware errata fix, remove that restriction
in the code, so both LBC SDRAM and SPD can be selected.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>