- 23 7月, 2015 10 次提交
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由 Stefan Roese 提交于
This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the Armada A38x boot image. Not linked with the main U-Boot. With this code addition and the serdes/PHY setup code, the Armada A38x support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Note: This code has undergone many hours (days!) of coding-style cleanup and refactoring. It still is not checkpatch clean though, I'm afraid. As the factoring of the code has so many levels of indentation that many lines are longer than 80 chars. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
With the upcoming addition of the Armada 38x DDR support, which is not compatible to the Armada XP DDR init code, we need to introduce a new directory infrastructure. To support multiple Marvell DDR controller. This will be the new structure: drivers/ddr/marvell/axp Supporting Armada XP (AXP) devices (and perhaps Armada 370) drivers/ddr/marvell/a38x Supporting Armada 38x devices (and perhaps Armada 39x) Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This code is ported from the Marvell bin_hdr code into mainline SPL U-Boot. It needs to be executed very early so that the devices connected to the serdes PHY are configured correctly. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
With the upcoming addition of the Armada 38x SPL support, which is not compatible to the Armada XP SERDES init code, we need to introduce a new directory infrastructure. So lets move the AXP serdes init code into a new directory. This way the A38x code can be added in a clean way. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
The u-boot-spl.kwb build target needs the SPL text-base (CONFIG_SPL_TEXT_BASE) as load and execution address. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Only with disabled MMU its possible to switch the base register address on Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also not accessible, as its still locked to cache. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Pin muxing needs to be done before UART output, since on A38x the UART pins need some re-muxing for output to work. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
On A38x switching the regs base address without running from SDRAM doesn't seem to work. So let the SPL still use the default base address and switch to the new address in the mail u-boot later. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Without calling timer_init(), the xdelay() functions return immediately. We need to call timer_init() early, so that these functions work and the PHY and DDR init code works correctly. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Anton Schubert <anton.schubert@gmx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Anton Schubert 提交于
This patch initializes the SATA address windows on Armada XP and allows it to work with the existing mvsata_ide driver. It also adds the necessary configuration for the db-mv784mp-gp board. Signed-off-by: NAnton Schubert <anton.schubert@gmx.de> Tested-by: NStefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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- 21 7月, 2015 30 次提交
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由 Zhichun Hua 提交于
When final MMU table is setup in DDR, TCR attributes must match those of the memroy for cacheability and shareability. Signed-off-by: NZhichun Hua <zhichun.hua@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 Zhichun Hua 提交于
For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit position [13:12] of TCR_ELx register. Signed-off-by: NZhichun Hua <zhichun.hua@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com>
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Freescale DSPI driver has been converted to Driver Model. The new driver depends on OF_CONTROL, DM, DM_SPI. This patch enable FSL_DSPI and its dependence configure options. Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
Enable DSPI flash related configurations for LS2085ARDB. Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
Enable DSPI flash related configurations. Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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DSPI has pin muxing with SDHC and other IPs, this patch check the value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check the "hwconfig" variable. If those pins are configured to DSPI and "hwconfig" enable DSPI, set the BRDCFG5 of QIXIS CPLD to configure the routing to on-board SPI memory. Otherwise will configure to SDHC. DSPI is enabled in "hwconfig" by appending "dspi", eg. setenv hwconfig "$hwconfig;dspi" Signed-off-by: NHaikun Wang <Haikun.Wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
DSPI has pin muxing with SDHC and other IPs, this patch check the value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check the "hwconfig" variable. If those pins are configured to DSPI and "hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure the routing to on-board SPI memory. Otherwise will configure to SDHC. DSPI is enabled in "hwconfig" by appending "dspi", eg. setenv hwconfig "$hwconfig;dspi" Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
Add dts source files for LS2085AQDS and LS2085ARDB boards. Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
Add DSPI controller dts node in fsl-ls2085a.dtsi Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
Bring in required device tree files for ls2085a from Linux. These are initially unchanged and have a number of pieces not needed by U-Boot. Signed-off-by: NHaikun Wang <Haikun.Wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
As SCFG_ENDIANCR register is added to choose little-endian or big-endian for audio IPs on Rev2.0 silion, little-endian mode is selected. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Wang Dongsheng 提交于
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform. Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K Signed-off-by: NWang Dongsheng <dongsheng.wang@freescale.com> Acked-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Wang Dongsheng 提交于
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well. Signed-off-by: NWang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
As the function 'sprintf' does not check buffer boundaries but outputs to the buffer 'enet' of fixed size (16), this patch removes the function 'sprintf', and uses 'strcpy' instead. It will assign the character arrays 'enet' and 'phy' the corresponding character strings. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Linux itb image size has been increased from 30MB. So updating kernel_size to 40MB in env variable. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Export functions required by Aquntia PHY firmware load application. functions are memset, strcpy, mdelay, mdio_get_current_dev, phy_find_by_mask, mdio_phydev_for_ethname and miiphy_set_current_dev Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Change infinite loop mechanism to timer based polling for QBMAN release in ldpaa_eth_rx. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Polling of TX conf frames is not a mandatory option. Packets can be transferred via WRIOP without TX conf frame. Configure ldpaa_eth driver to use TX path without confirmation frame Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Volatile command does not return frame immidiately, need to wait till a frame is available in DQRR. Ideally it should be a blocking call. Add timeout handling for DQRR frame instead of retry counter. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Do not immediately return if the enqueue function returns -EBUSY; re-try mulitple times. if timeout occures, release the buffer. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Stuart Yoder 提交于
This patch adds the infrastructure to update device tree nodes to convey SMMU stream IDs in the device tree. Fixups are implemented for PCI controllers initially. Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Stuart Yoder 提交于
delete any existing ICID pools in the DPC and create a new one based on the stream ID partitioning for the SoC Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Stuart Yoder 提交于
Stream IDs on ls2085a devices are not hardwired and are programmed by sw. There are a limited number of stream IDs available, and the partitioning of them is scenario dependent. This header defines the partitioning between legacy, PCI, and DPAA2 devices. Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Management complex major version should match to the firmware present in flash. Return error during mismatch of major version. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Update qbman driver - As per latest available qbman driver - Use of atomic APIs Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> CC: Geoff Thorpe <Geoff.Thorpe@freescale.com> CC: Haiying Wang <Haiying.Wang@freescale.com> CC: Roy Pledge <Roy.Pledge@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Update flibs changes to mc-0.6.0.1 for dpmang, dprc, dpni and dpio objects Also rename qbman_portal_ce/ci_paddr to qbman_portal_ce/ci_offset in dpio_attr. These are now offsets from the SoC QBMan portals base. Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 J. German Rivera 提交于
Load AIOP image from NOR flash into DDR so that the MC firmware the MC fw can start it at boot time Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Flush buffer before releasing to BMan after TX_conf to ensure, the core does not have any cachelines that the WRIOP will DMA to. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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