arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdr

This patch adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr)
into the Armada A38x boot image. Not linked with the main U-Boot. With this
code addition and the serdes/PHY setup code, the Armada A38x support
in mainline U-Boot is finally self-contained. So the complete image
for booting can be built from mainline U-Boot. Without any additional
external inclusion.

Note:
This code has undergone many hours (days!) of coding-style cleanup and
refactoring. It still is not checkpatch clean though, I'm afraid. As the
factoring of the code has so many levels of indentation that many lines
are longer than 80 chars.
Signed-off-by: NStefan Roese <sr@denx.de>

drivers/ddr/marvell/a38x/Makefile

+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD) += ddr3_a38x.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_a38x_training.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_debug.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_hws_hw_training.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_init.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training_bist.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training_centralization.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training_db.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training_hw_algo.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training_ip_engine.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training_leveling.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training_pbs.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training_static.o
+obj-$(CONFIG_SPL_BUILD) += xor.o

drivers/ddr/marvell/a38x/ddr3_a38x.c

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "ddr3_init.h"
+
+#define A38X_NUMBER_OF_INTERFACES	5
+
+#define SAR_DEV_ID_OFFS			27
+#define SAR_DEV_ID_MASK			0x7
+
+/* Termal Sensor Registers */
+#define TSEN_STATE_REG			0xe4070
+#define TSEN_STATE_OFFSET		31
+#define TSEN_STATE_MASK			(0x1 << TSEN_STATE_OFFSET)
+#define TSEN_CONF_REG			0xe4074
+#define TSEN_CONF_RST_OFFSET		8
+#define TSEN_CONF_RST_MASK		(0x1 << TSEN_CONF_RST_OFFSET)
+#define TSEN_STATUS_REG			0xe4078
+#define TSEN_STATUS_READOUT_VALID_OFFSET	10
+#define TSEN_STATUS_READOUT_VALID_MASK	(0x1 <<				\
+					 TSEN_STATUS_READOUT_VALID_OFFSET)
+#define TSEN_STATUS_TEMP_OUT_OFFSET	0
+#define TSEN_STATUS_TEMP_OUT_MASK	(0x3ff << TSEN_STATUS_TEMP_OUT_OFFSET)
+
+static struct dfx_access interface_map[] = {
+	/* Pipe	Client */
+	{ 0, 17 },
+	{ 1, 7 },
+	{ 1, 11 },
+	{ 0, 3 },
+	{ 1, 25 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 }
+};
+
+/* This array hold the board round trip delay (DQ and CK) per <interface,bus> */
+struct trip_delay_element a38x_board_round_trip_delay_array[] = {
+	/* 1st board */
+	/* Interface bus DQS-delay CK-delay */
+	{ 3952, 5060 },
+	{ 3192, 4493 },
+	{ 4785, 6677 },
+	{ 3413, 7267 },
+	{ 4282, 6086 },	/* ECC PUP */
+	{ 3952, 5134 },
+	{ 3192, 4567 },
+	{ 4785, 6751 },
+	{ 3413, 7341 },
+	{ 4282, 6160 },	/* ECC PUP */
+
+	/* 2nd board */
+	/* Interface bus DQS-delay CK-delay */
+	{ 3952, 5060 },
+	{ 3192, 4493 },
+	{ 4785, 6677 },
+	{ 3413, 7267 },
+	{ 4282, 6086 },	/* ECC PUP */
+	{ 3952, 5134 },
+	{ 3192, 4567 },
+	{ 4785, 6751 },
+	{ 3413, 7341 },
+	{ 4282, 6160 }	/* ECC PUP */
+};
+
+#ifdef STATIC_ALGO_SUPPORT
+/* package trace */
+static struct trip_delay_element a38x_package_round_trip_delay_array[] = {
+	/* IF BUS DQ_DELAY CK_DELAY */
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 },
+	{ 0, 0 }
+};
+
+static int a38x_silicon_delay_offset[] = {
+	/* board 0 */
+	0,
+	/* board 1 */
+	0,
+	/* board 2 */
+	0
+};
+#endif
+
+static u8 a38x_bw_per_freq[DDR_FREQ_LIMIT] = {
+	0x3,			/* DDR_FREQ_100 */
+	0x4,			/* DDR_FREQ_400 */
+	0x4,			/* DDR_FREQ_533 */
+	0x5,			/* DDR_FREQ_667 */
+	0x5,			/* DDR_FREQ_800 */
+	0x5,			/* DDR_FREQ_933 */
+	0x5,			/* DDR_FREQ_1066 */
+	0x3,			/* DDR_FREQ_311 */
+	0x3,			/* DDR_FREQ_333 */
+	0x4,			/* DDR_FREQ_467 */
+	0x5,			/* DDR_FREQ_850 */
+	0x5,			/* DDR_FREQ_600 */
+	0x3,			/* DDR_FREQ_300 */
+	0x5,			/* DDR_FREQ_900 */
+	0x3,			/* DDR_FREQ_360 */
+	0x5			/* DDR_FREQ_1000 */
+};
+
+static u8 a38x_rate_per_freq[DDR_FREQ_LIMIT] = {
+	 /*TBD*/ 0x1,		/* DDR_FREQ_100 */
+	0x2,			/* DDR_FREQ_400 */
+	0x2,			/* DDR_FREQ_533 */
+	0x2,			/* DDR_FREQ_667 */
+	0x2,			/* DDR_FREQ_800 */
+	0x3,			/* DDR_FREQ_933 */
+	0x3,			/* DDR_FREQ_1066 */
+	0x1,			/* DDR_FREQ_311 */
+	0x1,			/* DDR_FREQ_333 */
+	0x2,			/* DDR_FREQ_467 */
+	0x2,			/* DDR_FREQ_850 */
+	0x2,			/* DDR_FREQ_600 */
+	0x1,			/* DDR_FREQ_300 */
+	0x2,			/* DDR_FREQ_900 */
+	0x1,			/* DDR_FREQ_360 */
+	0x2			/* DDR_FREQ_1000 */
+};
+
+static u16 a38x_vco_freq_per_sar[] = {
+	666,			/* 0 */
+	1332,
+	800,
+	1600,
+	1066,
+	2132,
+	1200,
+	2400,
+	1332,
+	1332,
+	1500,
+	1500,
+	1600,			/* 12 */
+	1600,
+	1700,
+	1700,
+	1866,
+	1866,
+	1800,			/* 18 */
+	2000,
+	2000,
+	4000,
+	2132,
+	2132,
+	2300,
+	2300,
+	2400,
+	2400,
+	2500,
+	2500,
+	800
+};
+
+u32 pipe_multicast_mask;
+
+u32 dq_bit_map_2_phy_pin[] = {
+	1, 0, 2, 6, 9, 8, 3, 7,	/* 0 */
+	8, 9, 1, 7, 2, 6, 3, 0,	/* 1 */
+	3, 9, 7, 8, 1, 0, 2, 6,	/* 2 */
+	1, 0, 6, 2, 8, 3, 7, 9,	/* 3 */
+	0, 1, 2, 9, 7, 8, 3, 6,	/* 4 */
+};
+
+static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
+				     enum hws_ddr_freq freq);
+
+/*
+ * Read temperature TJ value
+ */
+u32 ddr3_ctrl_get_junc_temp(u8 dev_num)
+{
+	int reg = 0;
+
+	/* Initiates TSEN hardware reset once */
+	if ((reg_read(TSEN_CONF_REG) & TSEN_CONF_RST_MASK) == 0)
+		reg_bit_set(TSEN_CONF_REG, TSEN_CONF_RST_MASK);
+	mdelay(10);
+
+	/* Check if the readout field is valid */
+	if ((reg_read(TSEN_STATUS_REG) & TSEN_STATUS_READOUT_VALID_MASK) == 0) {
+		printf("%s: TSEN not ready\n", __func__);
+		return 0;
+	}
+
+	reg = reg_read(TSEN_STATUS_REG);
+	reg = (reg & TSEN_STATUS_TEMP_OUT_MASK) >> TSEN_STATUS_TEMP_OUT_OFFSET;
+
+	return ((((10000 * reg) / 21445) * 1000) - 272674) / 1000;
+}
+
+/*
+ * Name:     ddr3_tip_a38x_get_freq_config.
+ * Desc:
+ * Args:
+ * Notes:
+ * Returns:  MV_OK if success, other error code if fail.
+ */
+int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq,
+				  struct hws_tip_freq_config_info
+				  *freq_config_info)
+{
+	if (a38x_bw_per_freq[freq] == 0xff)
+		return MV_NOT_SUPPORTED;
+
+	if (freq_config_info == NULL)
+		return MV_BAD_PARAM;
+
+	freq_config_info->bw_per_freq = a38x_bw_per_freq[freq];
+	freq_config_info->rate_per_freq = a38x_rate_per_freq[freq];
+	freq_config_info->is_supported = 1;
+
+	return MV_OK;
+}
+
+/*
+ * Name:     ddr3_tip_a38x_pipe_enable.
+ * Desc:
+ * Args:
+ * Notes:
+ * Returns:  MV_OK if success, other error code if fail.
+ */
+int ddr3_tip_a38x_pipe_enable(u8 dev_num, enum hws_access_type interface_access,
+			      u32 if_id, int enable)
+{
+	u32 data_value, pipe_enable_mask = 0;
+
+	if (enable == 0) {
+		pipe_enable_mask = 0;
+	} else {
+		if (interface_access == ACCESS_TYPE_MULTICAST)
+			pipe_enable_mask = pipe_multicast_mask;
+		else
+			pipe_enable_mask = (1 << interface_map[if_id].pipe);
+	}
+
+	CHECK_STATUS(ddr3_tip_reg_read
+		     (dev_num, PIPE_ENABLE_ADDR, &data_value, MASK_ALL_BITS));
+	data_value = (data_value & (~0xff)) | pipe_enable_mask;
+	CHECK_STATUS(ddr3_tip_reg_write(dev_num, PIPE_ENABLE_ADDR, data_value));
+
+	return MV_OK;
+}
+
+/*
+ * Name:     ddr3_tip_a38x_if_write.
+ * Desc:
+ * Args:
+ * Notes:
+ * Returns:  MV_OK if success, other error code if fail.
+ */
+int ddr3_tip_a38x_if_write(u8 dev_num, enum hws_access_type interface_access,
+			   u32 if_id, u32 reg_addr, u32 data_value,
+			   u32 mask)
+{
+	u32 ui_data_read;
+
+	if (mask != MASK_ALL_BITS) {
+		CHECK_STATUS(ddr3_tip_a38x_if_read
+			     (dev_num, ACCESS_TYPE_UNICAST, if_id, reg_addr,
+			      &ui_data_read, MASK_ALL_BITS));
+		data_value = (ui_data_read & (~mask)) | (data_value & mask);
+	}
+
+	reg_write(reg_addr, data_value);
+
+	return MV_OK;
+}
+
+/*
+ * Name:     ddr3_tip_a38x_if_read.
+ * Desc:
+ * Args:
+ * Notes:
+ * Returns:  MV_OK if success, other error code if fail.
+ */
+int ddr3_tip_a38x_if_read(u8 dev_num, enum hws_access_type interface_access,
+			  u32 if_id, u32 reg_addr, u32 *data, u32 mask)
+{
+	*data = reg_read(reg_addr) & mask;
+
+	return MV_OK;
+}
+
+/*
+ * Name:     ddr3_tip_a38x_select_ddr_controller.
+ * Desc:     Enable/Disable access to Marvell's server.
+ * Args:     dev_num     - device number
+ *           enable        - whether to enable or disable the server
+ * Notes:
+ * Returns:  MV_OK if success, other error code if fail.
+ */
+int ddr3_tip_a38x_select_ddr_controller(u8 dev_num, int enable)
+{
+	u32 reg;
+
+	reg = reg_read(CS_ENABLE_REG);
+
+	if (enable)
+		reg |= (1 << 6);
+	else
+		reg &= ~(1 << 6);
+
+	reg_write(CS_ENABLE_REG, reg);
+
+	return MV_OK;
+}
+
+/*
+ * Name:     ddr3_tip_init_a38x_silicon.
+ * Desc:     init Training SW DB.
+ * Args:
+ * Notes:
+ * Returns:  MV_OK if success, other error code if fail.
+ */
+static int ddr3_tip_init_a38x_silicon(u32 dev_num, u32 board_id)
+{
+	struct hws_tip_config_func_db config_func;
+	enum hws_ddr_freq ddr_freq;
+	int status;
+	struct hws_topology_map *tm = ddr3_get_topology_map();
+
+	/* new read leveling version */
+	config_func.tip_dunit_read_func = ddr3_tip_a38x_if_read;
+	config_func.tip_dunit_write_func = ddr3_tip_a38x_if_write;
+	config_func.tip_dunit_mux_select_func =
+		ddr3_tip_a38x_select_ddr_controller;
+	config_func.tip_get_freq_config_info_func =
+		ddr3_tip_a38x_get_freq_config;
+	config_func.tip_set_freq_divider_func = ddr3_tip_a38x_set_divider;
+	config_func.tip_get_device_info_func = ddr3_tip_a38x_get_device_info;
+	config_func.tip_get_temperature = ddr3_ctrl_get_junc_temp;
+
+	ddr3_tip_init_config_func(dev_num, &config_func);
+
+	ddr3_tip_register_dq_table(dev_num, dq_bit_map_2_phy_pin);
+
+#ifdef STATIC_ALGO_SUPPORT
+	{
+		struct hws_tip_static_config_info static_config;
+		u32 board_offset =
+		    board_id * A38X_NUMBER_OF_INTERFACES *
+		    tm->num_of_bus_per_interface;
+
+		static_config.silicon_delay =
+			a38x_silicon_delay_offset[board_id];
+		static_config.package_trace_arr =
+			a38x_package_round_trip_delay_array;
+		static_config.board_trace_arr =
+			&a38x_board_round_trip_delay_array[board_offset];
+		ddr3_tip_init_static_config_db(dev_num, &static_config);
+	}
+#endif
+	status = ddr3_tip_a38x_get_init_freq(dev_num, &ddr_freq);
+	if (MV_OK != status) {
+		DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
+				      ("DDR3 silicon get target frequency - FAILED 0x%x\n",
+				       status));
+		return status;
+	}
+
+	rl_version = 1;
+	mask_tune_func = (SET_LOW_FREQ_MASK_BIT |
+			  LOAD_PATTERN_MASK_BIT |
+			  SET_MEDIUM_FREQ_MASK_BIT | WRITE_LEVELING_MASK_BIT |
+			  /* LOAD_PATTERN_2_MASK_BIT | */
+			  WRITE_LEVELING_SUPP_MASK_BIT |
+			  READ_LEVELING_MASK_BIT |
+			  PBS_RX_MASK_BIT |
+			  PBS_TX_MASK_BIT |
+			  SET_TARGET_FREQ_MASK_BIT |
+			  WRITE_LEVELING_TF_MASK_BIT |
+			  WRITE_LEVELING_SUPP_TF_MASK_BIT |
+			  READ_LEVELING_TF_MASK_BIT |
+			  CENTRALIZATION_RX_MASK_BIT |
+			  CENTRALIZATION_TX_MASK_BIT);
+	rl_mid_freq_wa = 1;
+
+	if ((ddr_freq == DDR_FREQ_333) || (ddr_freq == DDR_FREQ_400)) {
+		mask_tune_func = (WRITE_LEVELING_MASK_BIT |
+				  LOAD_PATTERN_2_MASK_BIT |
+				  WRITE_LEVELING_SUPP_MASK_BIT |
+				  READ_LEVELING_MASK_BIT |
+				  PBS_RX_MASK_BIT |
+				  PBS_TX_MASK_BIT |
+				  CENTRALIZATION_RX_MASK_BIT |
+				  CENTRALIZATION_TX_MASK_BIT);
+		rl_mid_freq_wa = 0; /* WA not needed if 333/400 is TF */
+	}
+
+	/* Supplementary not supported for ECC modes */
+	if (1 == ddr3_if_ecc_enabled()) {
+		mask_tune_func &= ~WRITE_LEVELING_SUPP_TF_MASK_BIT;
+		mask_tune_func &= ~WRITE_LEVELING_SUPP_MASK_BIT;
+		mask_tune_func &= ~PBS_TX_MASK_BIT;
+		mask_tune_func &= ~PBS_RX_MASK_BIT;
+	}
+
+	if (ck_delay == -1)
+		ck_delay = 160;
+	if (ck_delay_16 == -1)
+		ck_delay_16 = 160;
+	ca_delay = 0;
+	delay_enable = 1;
+
+	calibration_update_control = 1;
+
+	init_freq = tm->interface_params[first_active_if].memory_freq;
+
+	ddr3_tip_a38x_get_medium_freq(dev_num, &medium_freq);
+
+	return MV_OK;
+}
+
+int ddr3_a38x_update_topology_map(u32 dev_num, struct hws_topology_map *tm)
+{
+	u32 if_id = 0;
+	enum hws_ddr_freq freq;
+
+	ddr3_tip_a38x_get_init_freq(dev_num, &freq);
+	tm->interface_params[if_id].memory_freq = freq;
+
+	/*
+	 * re-calc topology parameters according to topology updates
+	 * (if needed)
+	 */
+	CHECK_STATUS(hws_ddr3_tip_load_topology_map(dev_num, tm));
+
+	return MV_OK;
+}
+
+int ddr3_tip_init_a38x(u32 dev_num, u32 board_id)
+{
+	struct hws_topology_map *tm = ddr3_get_topology_map();
+
+	if (NULL == tm)
+		return MV_FAIL;
+
+	ddr3_a38x_update_topology_map(dev_num, tm);
+	ddr3_tip_init_a38x_silicon(dev_num, board_id);
+
+	return MV_OK;
+}
+
+int ddr3_tip_a38x_get_init_freq(int dev_num, enum hws_ddr_freq *freq)
+{
+	u32 reg;
+
+	/* Read sample at reset setting */
+	reg = (reg_read(REG_DEVICE_SAR1_ADDR) >>
+	       RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) &
+		RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
+	switch (reg) {
+	case 0x0:
+	case 0x1:
+		*freq = DDR_FREQ_333;
+		break;
+	case 0x2:
+	case 0x3:
+		*freq = DDR_FREQ_400;
+		break;
+	case 0x4:
+	case 0xd:
+		*freq = DDR_FREQ_533;
+		break;
+	case 0x6:
+		*freq = DDR_FREQ_600;
+		break;
+	case 0x8:
+	case 0x11:
+	case 0x14:
+		*freq = DDR_FREQ_667;
+		break;
+	case 0xc:
+	case 0x15:
+	case 0x1b:
+		*freq = DDR_FREQ_800;
+		break;
+	case 0x10:
+		*freq = DDR_FREQ_933;
+		break;
+	case 0x12:
+		*freq = DDR_FREQ_900;
+		break;
+	case 0x13:
+		*freq = DDR_FREQ_900;
+		break;
+	default:
+		*freq = 0;
+		return MV_NOT_SUPPORTED;
+	}
+
+	return MV_OK;
+}
+
+int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq)
+{
+	u32 reg;
+
+	/* Read sample at reset setting */
+	reg = (reg_read(REG_DEVICE_SAR1_ADDR) >>
+	       RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) &
+		RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
+	switch (reg) {
+	case 0x0:
+	case 0x1:
+		/* Medium is same as TF to run PBS in this freq */
+		*freq = DDR_FREQ_333;
+		break;
+	case 0x2:
+	case 0x3:
+		/* Medium is same as TF to run PBS in this freq */
+		*freq = DDR_FREQ_400;
+		break;
+	case 0x4:
+	case 0xd:
+		*freq = DDR_FREQ_533;
+		break;
+	case 0x8:
+	case 0x11:
+	case 0x14:
+		*freq = DDR_FREQ_333;
+		break;
+	case 0xc:
+	case 0x15:
+	case 0x1b:
+		*freq = DDR_FREQ_400;
+		break;
+	case 0x6:
+		*freq = DDR_FREQ_300;
+		break;
+	case 0x12:
+		*freq = DDR_FREQ_360;
+		break;
+	case 0x13:
+		*freq = DDR_FREQ_400;
+		break;
+	default:
+		*freq = 0;
+		return MV_NOT_SUPPORTED;
+	}
+
+	return MV_OK;
+}
+
+u32 ddr3_tip_get_init_freq(void)
+{
+	enum hws_ddr_freq freq;
+
+	ddr3_tip_a38x_get_init_freq(0, &freq);
+
+	return freq;
+}
+
+static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
+				     enum hws_ddr_freq frequency)
+{
+	u32 divider = 0;
+	u32 sar_val;
+
+	if (if_id != 0) {
+		DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
+				      ("A38x does not support interface 0x%x\n",
+				       if_id));
+		return MV_BAD_PARAM;
+	}
+
+	/* get VCO freq index */
+	sar_val = (reg_read(REG_DEVICE_SAR1_ADDR) >>
+		   RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) &
+		RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
+	divider = a38x_vco_freq_per_sar[sar_val] / freq_val[frequency];
+
+	/* Set Sync mode */
+	CHECK_STATUS(ddr3_tip_a38x_if_write
+		     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x20220, 0x0,
+		      0x1000));
+	CHECK_STATUS(ddr3_tip_a38x_if_write
+		     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe42f4, 0x0,
+		      0x200));
+
+	/* cpupll_clkdiv_reset_mask */
+	CHECK_STATUS(ddr3_tip_a38x_if_write
+		     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0x1f,
+		      0xff));
+
+	/* cpupll_clkdiv_reload_smooth */
+	CHECK_STATUS(ddr3_tip_a38x_if_write
+		     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260,
+		      (0x2 << 8), (0xff << 8)));
+
+	/* cpupll_clkdiv_relax_en */
+	CHECK_STATUS(ddr3_tip_a38x_if_write
+		     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260,
+		      (0x2 << 24), (0xff << 24)));
+
+	/* write the divider */
+	CHECK_STATUS(ddr3_tip_a38x_if_write
+		     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4268,
+		      (divider << 8), (0x3f << 8)));
+
+	/* set cpupll_clkdiv_reload_ratio */
+	CHECK_STATUS(ddr3_tip_a38x_if_write
+		     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264,
+		      (1 << 8), (1 << 8)));
+
+	/* undet cpupll_clkdiv_reload_ratio */
+	CHECK_STATUS(ddr3_tip_a38x_if_write
+		     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0,
+		      (1 << 8)));
+
+	/* clear cpupll_clkdiv_reload_force */
+	CHECK_STATUS(ddr3_tip_a38x_if_write
+		     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260, 0,
+		      (0xff << 8)));
+
+	/* clear cpupll_clkdiv_relax_en */
+	CHECK_STATUS(ddr3_tip_a38x_if_write
+		     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260, 0,
+		      (0xff << 24)));
+
+	/* clear cpupll_clkdiv_reset_mask */
+	CHECK_STATUS(ddr3_tip_a38x_if_write
+		     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0,
+		      0xff));
+
+	/* Dunit training clock + 1:1 mode */
+	if ((frequency == DDR_FREQ_LOW_FREQ) || (freq_val[frequency] <= 400)) {
+		CHECK_STATUS(ddr3_tip_a38x_if_write
+			     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x18488,
+			      (1 << 16), (1 << 16)));
+		CHECK_STATUS(ddr3_tip_a38x_if_write
+			     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1524,
+			      (0 << 15), (1 << 15)));
+	} else {
+		CHECK_STATUS(ddr3_tip_a38x_if_write
+			     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x18488,
+			      0, (1 << 16)));
+		CHECK_STATUS(ddr3_tip_a38x_if_write
+			     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1524,
+			      (1 << 15), (1 << 15)));
+	}
+
+	return MV_OK;
+}
+
+/*
+ * external read from memory
+ */
+int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
+		      u32 num_of_bursts, u32 *data)
+{
+	u32 burst_num;
+
+	for (burst_num = 0; burst_num < num_of_bursts * 8; burst_num++)
+		data[burst_num] = readl(reg_addr + 4 * burst_num);
+
+	return MV_OK;
+}
+
+/*
+ * external write to memory
+ */
+int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
+		       u32 num_of_bursts, u32 *data) {
+	u32 burst_num;
+
+	for (burst_num = 0; burst_num < num_of_bursts * 8; burst_num++)
+		writel(data[burst_num], reg_addr + 4 * burst_num);
+
+	return MV_OK;
+}
+
+int ddr3_silicon_pre_init(void)
+{
+	int result;
+
+	result = ddr3_silicon_init();
+
+	return result;
+}
+
+int ddr3_post_run_alg(void)
+{
+	return MV_OK;
+}
+
+int ddr3_silicon_post_init(void)
+{
+	struct hws_topology_map *tm = ddr3_get_topology_map();
+
+	/* Set half bus width */
+	if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask)) {
+		CHECK_STATUS(ddr3_tip_if_write
+			     (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
+			      REG_SDRAM_CONFIG_ADDR, 0x0, 0x8000));
+	}
+
+	return MV_OK;
+}
+
+int ddr3_tip_a38x_get_device_info(u8 dev_num, struct ddr3_device_info *info_ptr)
+{
+	info_ptr->device_id = 0x6800;
+	info_ptr->ck_delay = ck_delay;
+
+	return MV_OK;
+}

drivers/ddr/marvell/a38x/ddr3_a38x.h

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _DDR3_A38X_H
+#define _DDR3_A38X_H
+
+#define MAX_INTERFACE_NUM		1
+#define MAX_BUS_NUM			5
+
+#include "ddr3_hws_hw_training_def.h"
+
+/* Allow topolgy update from board TWSI device*/
+#if !defined(CONFIG_CUSTOMER_BOARD_SUPPORT)
+#define MV_DDR_TOPOLOGY_UPDATE_FROM_TWSI
+#endif
+
+#define ECC_SUPPORT
+
+/* right now, we're not supporting this in mainline */
+#undef SUPPORT_STATIC_DUNIT_CONFIG
+
+/* Controler bus divider 1 for 32 bit, 2 for 64 bit */
+#define DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER	1
+
+/* Tune internal training params values */
+#define TUNE_TRAINING_PARAMS_CK_DELAY		160
+#define TUNE_TRAINING_PARAMS_CK_DELAY_16	160
+#define TUNE_TRAINING_PARAMS_PFINGER		41
+#define TUNE_TRAINING_PARAMS_NFINGER		43
+#define TUNE_TRAINING_PARAMS_PHYREG3VAL		0xa
+
+#define MARVELL_BOARD				MARVELL_BOARD_ID_BASE
+
+
+#define REG_DEVICE_SAR1_ADDR			0xe4204
+#define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET	17
+#define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK	0x1f
+
+/* DRAM Windows */
+#define REG_XBAR_WIN_5_CTRL_ADDR		0x20050
+#define REG_XBAR_WIN_5_BASE_ADDR		0x20054
+
+/* DRAM Windows */
+#define REG_XBAR_WIN_4_CTRL_ADDR                0x20040
+#define REG_XBAR_WIN_4_BASE_ADDR                0x20044
+#define REG_XBAR_WIN_4_REMAP_ADDR               0x20048
+#define REG_XBAR_WIN_7_REMAP_ADDR               0x20078
+#define REG_XBAR_WIN_16_CTRL_ADDR               0x200d0
+#define REG_XBAR_WIN_16_BASE_ADDR               0x200d4
+#define REG_XBAR_WIN_16_REMAP_ADDR              0x200dc
+#define REG_XBAR_WIN_19_CTRL_ADDR               0x200e8
+
+#define REG_FASTPATH_WIN_BASE_ADDR(win)         (0x20180 + (0x8 * win))
+#define REG_FASTPATH_WIN_CTRL_ADDR(win)         (0x20184 + (0x8 * win))
+
+/* SatR defined too change topology busWidth and ECC configuration */
+#define DDR_SATR_CONFIG_MASK_WIDTH		0x8
+#define DDR_SATR_CONFIG_MASK_ECC		0x10
+#define DDR_SATR_CONFIG_MASK_ECC_PUP		0x20
+
+#define	REG_SAMPLE_RESET_HIGH_ADDR		0x18600
+
+#define MV_BOARD_REFCLK				MV_BOARD_REFCLK_25MHZ
+
+/* Matrix enables DRAM modes (bus width/ECC) per boardId */
+#define TOPOLOGY_UPDATE_32BIT			0
+#define TOPOLOGY_UPDATE_32BIT_ECC		1
+#define TOPOLOGY_UPDATE_16BIT			2
+#define TOPOLOGY_UPDATE_16BIT_ECC		3
+#define TOPOLOGY_UPDATE_16BIT_ECC_PUP3		4
+#define TOPOLOGY_UPDATE { \
+		/* 32Bit, 32bit ECC, 16bit, 16bit ECC PUP4, 16bit ECC PUP3 */ \
+		{1, 1, 1, 1, 1},	/* RD_NAS_68XX_ID */ \
+		{1, 1, 1, 1, 1},	/* DB_68XX_ID	  */ \
+		{1, 0, 1, 0, 1},	/* RD_AP_68XX_ID  */ \
+		{1, 0, 1, 0, 1},	/* DB_AP_68XX_ID  */ \
+		{1, 0, 1, 0, 1},	/* DB_GP_68XX_ID  */ \
+		{0, 0, 1, 1, 0},	/* DB_BP_6821_ID  */ \
+		{1, 1, 1, 1, 1}		/* DB_AMC_6820_ID */ \
+	};
+
+enum {
+	CPU_1066MHZ_DDR_400MHZ,
+	CPU_RESERVED_DDR_RESERVED0,
+	CPU_667MHZ_DDR_667MHZ,
+	CPU_800MHZ_DDR_800MHZ,
+	CPU_RESERVED_DDR_RESERVED1,
+	CPU_RESERVED_DDR_RESERVED2,
+	CPU_RESERVED_DDR_RESERVED3,
+	LAST_FREQ
+};
+
+#define ACTIVE_INTERFACE_MASK			0x1
+
+#endif /* _DDR3_A38X_H */

drivers/ddr/marvell/a38x/ddr3_a38x_mc_static.h

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _DDR3_A38X_MC_STATIC_H
+#define _DDR3_A38X_MC_STATIC_H
+
+#include "ddr3_a38x.h"
+
+#ifdef SUPPORT_STATIC_DUNIT_CONFIG
+
+#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
+static struct reg_data ddr3_customer_800[] = {
+	/* parameters for customer board (based on 800MHZ) */
+	{0x1400,	0x7b00cc30, 0xffffffff},
+	{0x1404,	0x36301820, 0xffffffff},
+	{0x1408,	0x5415baab, 0xffffffff},
+	{0x140c,	0x38411def, 0xffffffff},
+	{0x1410,	0x18300000, 0xffffffff},
+	{0x1414,	0x00000700, 0xffffffff},
+	{0x1424,	0x0060f3ff, 0xffffffff},
+	{0x1428,	0x0011a940, 0xffffffff},
+	{0x142c,	0x28c5134,  0xffffffff},
+	{0x1474,	0x00000000, 0xffffffff},
+	{0x147c,	0x0000d771, 0xffffffff},
+	{0x1494,	0x00030000, 0xffffffff},
+	{0x149c,	0x00000300, 0xffffffff},
+	{0x14a8,	0x00000000, 0xffffffff},
+	{0x14cc,	0xbd09000d, 0xffffffff},
+	{0x1504,	0xfffffff1, 0xffffffff},
+	{0x150c,	0xffffffe5, 0xffffffff},
+	{0x1514,	0x00000000, 0xffffffff},
+	{0x151c,	0x00000000, 0xffffffff},
+	{0x1538,	0x00000b0b, 0xffffffff},
+	{0x153c,	0x00000c0c, 0xffffffff},
+	{0x15d0,	0x00000670, 0xffffffff},
+	{0x15d4,	0x00000046, 0xffffffff},
+	{0x15d8,	0x00000010, 0xffffffff},
+	{0x15dc,	0x00000000, 0xffffffff},
+	{0x15e0,	0x00000023, 0xffffffff},
+	{0x15e4,	0x00203c18, 0xffffffff},
+	{0x15ec,	0xf8000019, 0xffffffff},
+	{0x16a0,	0xcc000006, 0xffffffff},	/* Clock Delay */
+	{0xe4124,	0x08008073, 0xffffffff},	/* AVS BG default */
+	{0, 0, 0}
+};
+
+#else /* CONFIG_CUSTOMER_BOARD_SUPPORT */
+
+struct reg_data ddr3_a38x_933[MV_MAX_DDR3_STATIC_SIZE] = {
+	/* parameters for 933MHZ */
+	{0x1400,	0x7b00ce3a, 0xffffffff},
+	{0x1404,	0x36301820, 0xffffffff},
+	{0x1408,	0x7417eccf, 0xffffffff},
+	{0x140c,	0x3e421f98, 0xffffffff},
+	{0x1410,	0x1a300000, 0xffffffff},
+	{0x1414,	0x00000700, 0xffffffff},
+	{0x1424,	0x0060f3ff, 0xffffffff},
+	{0x1428,	0x0013ca50, 0xffffffff},
+	{0x142c,	0x028c5165, 0xffffffff},
+	{0x1474,	0x00000000, 0xffffffff},
+	{0x147c,	0x0000e871, 0xffffffff},
+	{0x1494,	0x00010000, 0xffffffff},
+	{0x149c,	0x00000001, 0xffffffff},
+	{0x14a8,	0x00000000, 0xffffffff},
+	{0x14cc,	0xbd09000d, 0xffffffff},
+	{0x1504,	0xffffffe1, 0xffffffff},
+	{0x150c,	0xffffffe5, 0xffffffff},
+	{0x1514,	0x00000000, 0xffffffff},
+	{0x151c,	0x00000000, 0xffffffff},
+	{0x1538,	0x00000d0d, 0xffffffff},
+	{0x153c,	0x00000d0d, 0xffffffff},
+	{0x15d0,	0x00000608, 0xffffffff},
+	{0x15d4,	0x00000044, 0xffffffff},
+	{0x15d8,	0x00000020, 0xffffffff},
+	{0x15dc,	0x00000000, 0xffffffff},
+	{0x15e0,	0x00000021, 0xffffffff},
+	{0x15e4,	0x00203c18, 0xffffffff},
+	{0x15ec,	0xf8000019, 0xffffffff},
+	{0x16a0,	0xcc000006, 0xffffffff},	/* Clock Delay */
+	{0xe4124,	0x08008073, 0xffffffff},	/* AVS BG default */
+	{0, 0, 0}
+};
+
+static struct reg_data ddr3_a38x_800[] = {
+	/* parameters for 800MHZ */
+	{0x1400,	0x7b00cc30, 0xffffffff},
+	{0x1404,	0x36301820, 0xffffffff},
+	{0x1408,	0x5415baab, 0xffffffff},
+	{0x140c,	0x38411def, 0xffffffff},
+	{0x1410,	0x18300000, 0xffffffff},
+	{0x1414,	0x00000700, 0xffffffff},
+	{0x1424,	0x0060f3ff, 0xffffffff},
+	{0x1428,	0x0011a940, 0xffffffff},
+	{0x142c,	0x28c5134,  0xffffffff},
+	{0x1474,	0x00000000, 0xffffffff},
+	{0x147c,	0x0000d771, 0xffffffff},
+	{0x1494,	0x00030000, 0xffffffff},
+	{0x149c,	0x00000300, 0xffffffff},
+	{0x14a8,	0x00000000, 0xffffffff},
+	{0x14cc,	0xbd09000d, 0xffffffff},
+	{0x1504,	0xfffffff1, 0xffffffff},
+	{0x150c,	0xffffffe5, 0xffffffff},
+	{0x1514,	0x00000000, 0xffffffff},
+	{0x151c,	0x00000000, 0xffffffff},
+	{0x1538,	0x00000b0b, 0xffffffff},
+	{0x153c,	0x00000c0c, 0xffffffff},
+	{0x15d0,	0x00000670, 0xffffffff},
+	{0x15d4,	0x00000046, 0xffffffff},
+	{0x15d8,	0x00000010, 0xffffffff},
+	{0x15dc,	0x00000000, 0xffffffff},
+	{0x15e0,	0x00000023, 0xffffffff},
+	{0x15e4,	0x00203c18, 0xffffffff},
+	{0x15ec,	0xf8000019, 0xffffffff},
+	{0x16a0,	0xcc000006, 0xffffffff},	/* Clock Delay */
+	{0xe4124,	0x08008073, 0xffffffff},	/* AVS BG default */
+	{0,   0, 0}
+};
+
+static struct reg_data ddr3_a38x_667[] = {
+	/* parameters for 667MHZ */
+	/* DDR SDRAM Configuration Register */
+	{0x1400,    0x7b00ca28, 0xffffffff},
+	/* Dunit Control Low Register - kw28 bit12 low (disable CLK1) */
+	{0x1404,    0x36301820, 0xffffffff},
+	/* DDR SDRAM Timing (Low) Register */
+	{0x1408,    0x43149997, 0xffffffff},
+	/* DDR SDRAM Timing (High) Register */
+	{0x140c,    0x38411bc7, 0xffffffff},
+	/* DDR SDRAM Address Control Register */
+	{0x1410,    0x14330000, 0xffffffff},
+	/* DDR SDRAM Open Pages Control Register */
+	{0x1414,    0x00000700, 0xffffffff},
+	/* Dunit Control High Register (2 :1 - bits 15:12 = 0xd) */
+	{0x1424,    0x0060f3ff, 0xffffffff},
+	/* Dunit Control High Register */
+	{0x1428,    0x000f8830, 0xffffffff},
+	/* Dunit Control High Register  (2:1 -  bit 29 = '1') */
+	{0x142c,    0x28c50f8,  0xffffffff},
+	{0x147c,    0x0000c671, 0xffffffff},
+	/* DDR SDRAM ODT Control (Low) Register */
+	{0x1494,    0x00030000, 0xffffffff},
+	/* DDR SDRAM ODT Control (High) Register, will be configured at WL */
+	{0x1498,    0x00000000, 0xffffffff},
+	/* DDR Dunit ODT Control Register */
+	{0x149c,    0x00000300, 0xffffffff},
+	{0x14a8,    0x00000000, 0xffffffff}, /*  */
+	{0x14cc,    0xbd09000d, 0xffffffff}, /*  */
+	{0x1474,    0x00000000, 0xffffffff},
+	/* Read Data Sample Delays Register */
+	{0x1538,    0x00000009, 0xffffffff},
+	/* Read Data Ready Delay Register */
+	{0x153c,    0x0000000c, 0xffffffff},
+	{0x1504,    0xfffffff1, 0xffffffff}, /*  */
+	{0x150c,    0xffffffe5, 0xffffffff}, /*  */
+	{0x1514,    0x00000000, 0xffffffff}, /*  */
+	{0x151c,    0x0,	0xffffffff}, /*  */
+	{0x15d0,    0x00000650, 0xffffffff}, /* MR0 */
+	{0x15d4,    0x00000046, 0xffffffff}, /* MR1 */
+	{0x15d8,    0x00000010, 0xffffffff}, /* MR2 */
+	{0x15dc,    0x00000000, 0xffffffff}, /* MR3 */
+	{0x15e0,    0x23,	0xffffffff}, /*  */
+	{0x15e4,    0x00203c18, 0xffffffff}, /* ZQC Configuration Register */
+	{0x15ec,    0xf8000019, 0xffffffff}, /* DDR PHY */
+	{0x16a0,    0xcc000006, 0xffffffff}, /* Clock Delay */
+	{0xe4124,   0x08008073, 0xffffffff}, /* AVS BG default */
+	{0, 0, 0}
+};
+
+static struct reg_data ddr3_a38x_533[] = {
+	/* parameters for 533MHZ */
+	/* DDR SDRAM Configuration Register */
+	{0x1400,    0x7b00d040, 0xffffffff},
+	/* Dunit Control Low Register - kw28 bit12 low (disable CLK1) */
+	{0x1404,    0x36301820, 0xffffffff},
+	/* DDR SDRAM Timing (Low) Register */
+	{0x1408,    0x33137772, 0xffffffff},
+	/* DDR SDRAM Timing (High) Register */
+	{0x140c,    0x3841199f, 0xffffffff},
+	/* DDR SDRAM Address Control Register */
+	{0x1410,    0x10330000, 0xffffffff},
+	/* DDR SDRAM Open Pages Control Register */
+	{0x1414,    0x00000700, 0xffffffff},
+	/* Dunit Control High Register (2 :1 - bits 15:12 = 0xd) */
+	{0x1424,    0x0060f3ff, 0xffffffff},
+	/* Dunit Control High Register */
+	{0x1428,    0x000d6720, 0xffffffff},
+	/* Dunit Control High Register  (2:1 -  bit 29 = '1') */
+	{0x142c,    0x028c50c3, 0xffffffff},
+	{0x147c,    0x0000b571, 0xffffffff},
+	/* DDR SDRAM ODT Control (Low) Register */
+	{0x1494,    0x00030000, 0xffffffff},
+	/* DDR SDRAM ODT Control (High) Register, will be configured at WL */
+	{0x1498,    0x00000000, 0xffffffff},
+	/* DDR Dunit ODT Control Register */
+	{0x149c,    0x00000003, 0xffffffff},
+	{0x14a8,    0x00000000, 0xffffffff}, /*  */
+	{0x14cc,    0xbd09000d, 0xffffffff}, /*  */
+	{0x1474,    0x00000000, 0xffffffff},
+	/* Read Data Sample Delays Register */
+	{0x1538,    0x00000707, 0xffffffff},
+	/* Read Data Ready Delay Register */
+	{0x153c,    0x00000707, 0xffffffff},
+	{0x1504,    0xffffffe1, 0xffffffff}, /*  */
+	{0x150c,    0xffffffe5, 0xffffffff}, /*  */
+	{0x1514,    0x00000000, 0xffffffff}, /*  */
+	{0x151c,    0x00000000,	0xffffffff}, /*  */
+	{0x15d0,    0x00000630, 0xffffffff}, /* MR0 */
+	{0x15d4,    0x00000046, 0xffffffff}, /* MR1 */
+	{0x15d8,    0x00000008, 0xffffffff}, /* MR2 */
+	{0x15dc,    0x00000000, 0xffffffff}, /* MR3 */
+	{0x15e0,    0x00000023,	0xffffffff}, /*  */
+	{0x15e4,    0x00203c18, 0xffffffff}, /* ZQC Configuration Register */
+	{0x15ec,    0xf8000019, 0xffffffff}, /* DDR PHY */
+	{0x16a0,    0xcc000006, 0xffffffff}, /* Clock Delay */
+	{0xe4124,   0x08008073, 0xffffffff}, /* AVS BG default */
+	{0, 0, 0}
+};
+
+#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */
+
+#endif /* SUPPORT_STATIC_DUNIT_CONFIG */
+
+#endif /* _DDR3_A38X_MC_STATIC_H */

drivers/ddr/marvell/a38x/ddr3_a38x_topology.h

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _DDR3_A38X_TOPOLOGY_H
+#define _DDR3_A38X_TOPOLOGY_H
+
+#include "ddr_topology_def.h"
+
+/* Bus mask variants */
+#define BUS_MASK_32BIT			0xf
+#define BUS_MASK_32BIT_ECC		0x1f
+#define BUS_MASK_16BIT			0x3
+#define BUS_MASK_16BIT_ECC		0x13
+#define BUS_MASK_16BIT_ECC_PUP3		0xb
+
+#define DYNAMIC_CS_SIZE_CONFIG
+#define DISABLE_L2_FILTERING_DURING_DDR_TRAINING
+
+#endif /* _DDR3_A38X_TOPOLOGY_H */

drivers/ddr/marvell/a38x/ddr3_a38x_training.c

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "ddr3_init.h"
+
+/*
+ * Name:     ddr3_tip_init_silicon
+ * Desc:     initiate silicon parameters
+ * Args:
+ * Notes:
+ * Returns:  required value
+ */
+int ddr3_silicon_init(void)
+{
+	int status;
+	static int init_done;
+
+	if (init_done == 1)
+		return MV_OK;
+
+	status = ddr3_tip_init_a38x(0, 0);
+	if (MV_OK != status) {
+		printf("DDR3 A38x silicon init - FAILED 0x%x\n", status);
+		return status;
+	}
+
+	init_done = 1;
+
+	return MV_OK;
+}

drivers/ddr/marvell/a38x/ddr3_hws_hw_training.c

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "ddr3_init.h"
+
+#define REG_READ_DATA_SAMPLE_DELAYS_ADDR	0x1538
+#define REG_READ_DATA_SAMPLE_DELAYS_MASK	0x1f
+#define REG_READ_DATA_SAMPLE_DELAYS_OFFS	8
+
+#define REG_READ_DATA_READY_DELAYS_ADDR		0x153c
+#define REG_READ_DATA_READY_DELAYS_MASK		0x1f
+#define REG_READ_DATA_READY_DELAYS_OFFS		8
+
+int ddr3_if_ecc_enabled(void)
+{
+	struct hws_topology_map *tm = ddr3_get_topology_map();
+
+	if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) ||
+	    DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))
+		return 1;
+	else
+		return 0;
+}
+
+int ddr3_pre_algo_config(void)
+{
+	struct hws_topology_map *tm = ddr3_get_topology_map();
+
+	/* Set Bus3 ECC training mode */
+	if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) {
+		/* Set Bus3 ECC MUX */
+		CHECK_STATUS(ddr3_tip_if_write
+			     (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
+			      REG_SDRAM_PINS_MUX, 0x100, 0x100));
+	}
+
+	/* Set regular ECC training mode (bus4 and bus 3) */
+	if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) ||
+	    (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))) {
+		/* Enable ECC Write MUX */
+		CHECK_STATUS(ddr3_tip_if_write
+			     (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
+			      TRAINING_SW_2_REG, 0x100, 0x100));
+		/* General ECC enable */
+		CHECK_STATUS(ddr3_tip_if_write
+			     (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
+			      REG_SDRAM_CONFIG_ADDR, 0x40000, 0x40000));
+		/* Disable Read Data ECC MUX */
+		CHECK_STATUS(ddr3_tip_if_write
+			     (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
+			      TRAINING_SW_2_REG, 0x0, 0x2));
+	}
+
+	return MV_OK;
+}
+
+int ddr3_post_algo_config(void)
+{
+	struct hws_topology_map *tm = ddr3_get_topology_map();
+	int status;
+
+	status = ddr3_post_run_alg();
+	if (MV_OK != status) {
+		printf("DDR3 Post Run Alg - FAILED 0x%x\n", status);
+		return status;
+	}
+
+	/* Un_set ECC training mode */
+	if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) ||
+	    (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))) {
+		/* Disable ECC Write MUX */
+		CHECK_STATUS(ddr3_tip_if_write
+			     (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
+			      TRAINING_SW_2_REG, 0x0, 0x100));
+		/* General ECC and Bus3 ECC MUX remains enabled */
+	}
+
+	return MV_OK;
+}
+
+int ddr3_hws_hw_training(void)
+{
+	enum hws_algo_type algo_mode = ALGO_TYPE_DYNAMIC;
+	int status;
+	struct init_cntr_param init_param;
+
+	status = ddr3_silicon_pre_init();
+	if (MV_OK != status) {
+		printf("DDR3 Pre silicon Config - FAILED 0x%x\n", status);
+		return status;
+	}
+
+	init_param.do_mrs_phy = 1;
+#if defined(CONFIG_ARMADA_38X)  || defined(CONFIG_ARMADA_39X)
+	init_param.is_ctrl64_bit = 0;
+#else
+	init_param.is_ctrl64_bit = 1;
+#endif
+#if defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_38X) || \
+	defined(CONFIG_ARMADA_39X)
+	init_param.init_phy = 1;
+#else
+	init_param.init_phy = 0;
+#endif
+	init_param.msys_init = 1;
+	status = hws_ddr3_tip_init_controller(0, &init_param);
+	if (MV_OK != status) {
+		printf("DDR3 init controller - FAILED 0x%x\n", status);
+		return status;
+	}
+
+	status = ddr3_silicon_post_init();
+	if (MV_OK != status) {
+		printf("DDR3 Post Init - FAILED 0x%x\n", status);
+		return status;
+	}
+
+	status = ddr3_pre_algo_config();
+	if (MV_OK != status) {
+		printf("DDR3 Pre Algo Config - FAILED 0x%x\n", status);
+		return status;
+	}
+
+	/* run algorithm in order to configure the PHY */
+	status = hws_ddr3_tip_run_alg(0, algo_mode);
+	if (MV_OK != status) {
+		printf("DDR3 run algorithm - FAILED 0x%x\n", status);
+		return status;
+	}
+
+	status = ddr3_post_algo_config();
+	if (MV_OK != status) {
+		printf("DDR3 Post Algo Config - FAILED 0x%x\n", status);
+		return status;
+	}
+
+	return MV_OK;
+}

drivers/ddr/marvell/a38x/ddr3_hws_hw_training.h

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _DDR3_HWS_HW_TRAINING_H
+#define _DDR3_HWS_HW_TRAINING_H
+
+/* struct used for DLB configuration array */
+struct dlb_config {
+	u32 reg_addr;
+	u32 reg_data;
+};
+
+/* Topology update structure */
+struct topology_update_info {
+	int	update_ecc;
+	u8	ecc;
+	int	update_width;
+	u8	width;
+	int	update_ecc_pup3_mode;
+	u8	ecc_pup_mode_offset;
+};
+
+/* Topology update defines */
+#define TOPOLOGY_UPDATE_WIDTH_16BIT		1
+#define TOPOLOGY_UPDATE_WIDTH_32BIT		0
+#define TOPOLOGY_UPDATE_WIDTH_32BIT_MASK	0xf
+#define TOPOLOGY_UPDATE_WIDTH_16BIT_MASK	0x3
+
+#define TOPOLOGY_UPDATE_ECC_ON			1
+#define TOPOLOGY_UPDATE_ECC_OFF			0
+#define TOPOLOGY_UPDATE_ECC_OFFSET_PUP4		4
+#define TOPOLOGY_UPDATE_ECC_OFFSET_PUP3		3
+
+/*
+ * 1. L2 filter should be set at binary header to 0xd000000,
+ *    to avoid conflict with internal register IO.
+ * 2. U-Boot modifies internal registers base to 0xf100000,
+ *    and than should update L2 filter accordingly to 0xf000000 (3.75 GB)
+ */
+/* temporary limit l2 filter to 3GiB (LSP issue) */
+#define L2_FILTER_FOR_MAX_MEMORY_SIZE 0xc0000000
+#define ADDRESS_FILTERING_END_REGISTER 0x8c04
+
+#define SUB_VERSION	0
+
+#endif /* _DDR3_HWS_HW_TRAINING_H */

drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _DDR3_HWS_HW_TRAINING_DEF_H
+#define _DDR3_HWS_HW_TRAINING_DEF_H
+
+#define SAR_DDR3_FREQ_MASK		0xfe00000
+#define SAR_CPU_FAB_GET(cpu, fab)	(((cpu & 0x7) << 21) | \
+					 ((fab & 0xf) << 24))
+
+#define MAX_CS				4
+
+#define MIN_DIMM_ADDR			0x50
+#define FAR_END_DIMM_ADDR		0x50
+#define MAX_DIMM_ADDR			0x60
+
+#define SDRAM_CS_SIZE			0xfffffff
+#define SDRAM_CS_BASE			0x0
+#define SDRAM_DIMM_SIZE			0x80000000
+
+#define CPU_CONFIGURATION_REG(id)	(0x21800 + (id * 0x100))
+#define CPU_MRVL_ID_OFFSET		0x10
+#define SAR1_CPU_CORE_MASK		0x00000018
+#define SAR1_CPU_CORE_OFFSET		3
+
+#define NEW_FABRIC_TWSI_ADDR		0x4e
+#ifdef DB_784MP_GP
+#define BUS_WIDTH_ECC_TWSI_ADDR		0x4e
+#else
+#define BUS_WIDTH_ECC_TWSI_ADDR		0x4f
+#endif
+#define MV_MAX_DDR3_STATIC_SIZE		50
+#define MV_DDR3_MODES_NUMBER		30
+
+#define RESUME_RL_PATTERNS_ADDR		0xfe0000
+#define RESUME_RL_PATTERNS_SIZE		0x100
+#define RESUME_TRAINING_VALUES_ADDR	(RESUME_RL_PATTERNS_ADDR + \
+					 RESUME_RL_PATTERNS_SIZE)
+#define RESUME_TRAINING_VALUES_MAX	0xcd0
+#define BOOT_INFO_ADDR			(RESUME_RL_PATTERNS_ADDR + 0x1000)
+#define CHECKSUM_RESULT_ADDR		(BOOT_INFO_ADDR + 0x1000)
+#define NUM_OF_REGISTER_ADDR		(CHECKSUM_RESULT_ADDR + 4)
+#define SUSPEND_MAGIC_WORD		0xdeadb002
+#define REGISTER_LIST_END		0xffffffff
+
+/* MISC */
+#define INTER_REGS_BASE			SOC_REGS_PHY_BASE
+
+/* DDR */
+#define REG_SDRAM_CONFIG_ADDR			0x1400
+#define REG_SDRAM_CONFIG_MASK			0x9fffffff
+#define REG_SDRAM_CONFIG_RFRS_MASK		0x3fff
+#define REG_SDRAM_CONFIG_WIDTH_OFFS		15
+#define REG_SDRAM_CONFIG_REGDIMM_OFFS		17
+#define REG_SDRAM_CONFIG_ECC_OFFS		18
+#define REG_SDRAM_CONFIG_IERR_OFFS		19
+#define REG_SDRAM_CONFIG_PUPRSTDIV_OFFS		28
+#define REG_SDRAM_CONFIG_RSTRD_OFFS		30
+
+#define REG_SDRAM_PINS_MUX			0x19d4
+
+#define REG_DUNIT_CTRL_LOW_ADDR			0x1404
+#define REG_DUNIT_CTRL_LOW_2T_OFFS		3
+#define REG_DUNIT_CTRL_LOW_2T_MASK		0x3
+#define REG_DUNIT_CTRL_LOW_DPDE_OFFS		14
+
+#define REG_SDRAM_TIMING_LOW_ADDR		0x1408
+#define REG_SDRAM_TIMING_HIGH_ADDR		0x140c
+#define REG_SDRAM_TIMING_H_R2R_OFFS		7
+#define REG_SDRAM_TIMING_H_R2R_MASK		0x3
+#define REG_SDRAM_TIMING_H_R2W_W2R_OFFS		9
+#define REG_SDRAM_TIMING_H_R2W_W2R_MASK		0x3
+#define REG_SDRAM_TIMING_H_W2W_OFFS		11
+#define REG_SDRAM_TIMING_H_W2W_MASK		0x1f
+#define REG_SDRAM_TIMING_H_R2R_H_OFFS		19
+#define REG_SDRAM_TIMING_H_R2R_H_MASK		0x7
+#define REG_SDRAM_TIMING_H_R2W_W2R_H_OFFS	22
+#define REG_SDRAM_TIMING_H_R2W_W2R_H_MASK	0x7
+
+#define REG_SDRAM_ADDRESS_CTRL_ADDR		0x1410
+#define REG_SDRAM_ADDRESS_SIZE_OFFS		2
+#define REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS	18
+#define REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS	4
+
+#define REG_SDRAM_OPEN_PAGES_ADDR		0x1414
+#define REG_SDRAM_OPERATION_CS_OFFS		8
+
+#define REG_SDRAM_OPERATION_ADDR		0x1418
+#define REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS	24
+#define REG_SDRAM_OPERATION_CWA_DATA_OFFS	20
+#define REG_SDRAM_OPERATION_CWA_DATA_MASK	0xf
+#define REG_SDRAM_OPERATION_CWA_RC_OFFS		16
+#define REG_SDRAM_OPERATION_CWA_RC_MASK		0xf
+#define REG_SDRAM_OPERATION_CMD_MR0		0xf03
+#define REG_SDRAM_OPERATION_CMD_MR1		0xf04
+#define REG_SDRAM_OPERATION_CMD_MR2		0xf08
+#define REG_SDRAM_OPERATION_CMD_MR3		0xf09
+#define REG_SDRAM_OPERATION_CMD_RFRS		0xf02
+#define REG_SDRAM_OPERATION_CMD_CWA		0xf0e
+#define REG_SDRAM_OPERATION_CMD_RFRS_DONE	0xf
+#define REG_SDRAM_OPERATION_CMD_MASK		0xf
+#define REG_SDRAM_OPERATION_CS_OFFS		8
+
+#define REG_OUDDR3_TIMING_ADDR			0x142c
+
+#define REG_SDRAM_MODE_ADDR			0x141c
+
+#define REG_SDRAM_EXT_MODE_ADDR			0x1420
+
+#define REG_DDR_CONT_HIGH_ADDR			0x1424
+
+#define REG_ODT_TIME_LOW_ADDR			0x1428
+#define REG_ODT_ON_CTL_RD_OFFS                  12
+#define REG_ODT_OFF_CTL_RD_OFFS                 16
+#define REG_SDRAM_ERROR_ADDR                    0x1454
+#define REG_SDRAM_AUTO_PWR_SAVE_ADDR            0x1474
+#define REG_ODT_TIME_HIGH_ADDR			0x147c
+
+#define REG_SDRAM_INIT_CTRL_ADDR		0x1480
+#define REG_SDRAM_INIT_CTRL_OFFS		0
+#define REG_SDRAM_INIT_CKE_ASSERT_OFFS		2
+#define REG_SDRAM_INIT_RESET_DEASSERT_OFFS	3
+#define REG_SDRAM_INIT_RESET_MASK_OFFS		1
+
+#define REG_SDRAM_ODT_CTRL_LOW_ADDR		0x1494
+
+#define REG_SDRAM_ODT_CTRL_HIGH_ADDR		0x1498
+#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK	0x0
+#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_ENA	0x3
+
+#define REG_DUNIT_ODT_CTRL_ADDR			0x149c
+#define REG_DUNIT_ODT_CTRL_OVRD_OFFS            8
+#define REG_DUNIT_ODT_CTRL_OVRD_VAL_OFFS        9
+
+#define REG_DRAM_FIFO_CTRL_ADDR			0x14a0
+
+#define REG_DRAM_AXI_CTRL_ADDR			0x14a8
+#define REG_DRAM_AXI_CTRL_AXIDATABUSWIDTH_OFFS	0
+
+#define REG_METAL_MASK_ADDR			0x14b0
+#define REG_METAL_MASK_MASK			0xdfffffff
+#define REG_METAL_MASK_RETRY_OFFS		0
+
+#define REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR	0x14c0
+
+#define REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR	0x14c4
+#define REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR      0x14c8
+#define REG_DRAM_MAIN_PADS_CAL_ADDR		0x14cc
+
+#define REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR      0x17c8
+
+#define REG_CS_SIZE_SCRATCH_ADDR		0x1504
+#define REG_DYNAMIC_POWER_SAVE_ADDR             0x1520
+#define REG_DDR_IO_ADDR				0x1524
+#define REG_DDR_IO_CLK_RATIO_OFFS		15
+
+#define REG_DFS_ADDR				0x1528
+#define REG_DFS_DLLNEXTSTATE_OFFS		0
+#define REG_DFS_BLOCK_OFFS			1
+#define REG_DFS_SR_OFFS				2
+#define REG_DFS_ATSR_OFFS			3
+#define REG_DFS_RECONF_OFFS			4
+#define REG_DFS_CL_NEXT_STATE_OFFS		8
+#define REG_DFS_CL_NEXT_STATE_MASK		0xf
+#define REG_DFS_CWL_NEXT_STATE_OFFS		12
+#define REG_DFS_CWL_NEXT_STATE_MASK		0x7
+
+#define REG_READ_DATA_SAMPLE_DELAYS_ADDR	0x1538
+#define REG_READ_DATA_SAMPLE_DELAYS_MASK	0x1f
+#define REG_READ_DATA_SAMPLE_DELAYS_OFFS	8
+
+#define REG_READ_DATA_READY_DELAYS_ADDR		0x153c
+#define REG_READ_DATA_READY_DELAYS_MASK		0x1f
+#define REG_READ_DATA_READY_DELAYS_OFFS		8
+
+#define START_BURST_IN_ADDR			1
+
+#define REG_DRAM_TRAINING_SHADOW_ADDR		0x18488
+#define REG_DRAM_TRAINING_ADDR			0x15b0
+#define REG_DRAM_TRAINING_LOW_FREQ_OFFS		0
+#define REG_DRAM_TRAINING_PATTERNS_OFFS		4
+#define REG_DRAM_TRAINING_MED_FREQ_OFFS		2
+#define REG_DRAM_TRAINING_WL_OFFS		3
+#define REG_DRAM_TRAINING_RL_OFFS		6
+#define REG_DRAM_TRAINING_DQS_RX_OFFS		15
+#define REG_DRAM_TRAINING_DQS_TX_OFFS		16
+#define REG_DRAM_TRAINING_CS_OFFS		20
+#define REG_DRAM_TRAINING_RETEST_OFFS		24
+#define REG_DRAM_TRAINING_DFS_FREQ_OFFS		27
+#define REG_DRAM_TRAINING_DFS_REQ_OFFS		29
+#define REG_DRAM_TRAINING_ERROR_OFFS		30
+#define REG_DRAM_TRAINING_AUTO_OFFS		31
+#define REG_DRAM_TRAINING_RETEST_PAR		0x3
+#define REG_DRAM_TRAINING_RETEST_MASK		0xf8ffffff
+#define REG_DRAM_TRAINING_CS_MASK		0xff0fffff
+#define REG_DRAM_TRAINING_PATTERNS_MASK		0xff0f0000
+
+#define REG_DRAM_TRAINING_1_ADDR		0x15b4
+#define REG_DRAM_TRAINING_1_TRNBPOINT_OFFS	16
+
+#define REG_DRAM_TRAINING_2_ADDR		0x15b8
+#define REG_DRAM_TRAINING_2_OVERRUN_OFFS	17
+#define REG_DRAM_TRAINING_2_FIFO_RST_OFFS	4
+#define REG_DRAM_TRAINING_2_RL_MODE_OFFS	3
+#define REG_DRAM_TRAINING_2_WL_MODE_OFFS	2
+#define REG_DRAM_TRAINING_2_ECC_MUX_OFFS	1
+#define REG_DRAM_TRAINING_2_SW_OVRD_OFFS	0
+
+#define REG_DRAM_TRAINING_PATTERN_BASE_ADDR	0x15bc
+#define REG_DRAM_TRAINING_PATTERN_BASE_OFFS	3
+
+#define REG_TRAINING_DEBUG_2_ADDR		0x15c4
+#define REG_TRAINING_DEBUG_2_OFFS		16
+#define REG_TRAINING_DEBUG_2_MASK		0x3
+
+#define REG_TRAINING_DEBUG_3_ADDR		0x15c8
+#define REG_TRAINING_DEBUG_3_OFFS		3
+#define REG_TRAINING_DEBUG_3_MASK		0x7
+
+#define	MR_CS_ADDR_OFFS				4
+
+#define	REG_DDR3_MR0_ADDR			0x15d0
+#define	REG_DDR3_MR0_CS_ADDR			0x1870
+#define REG_DDR3_MR0_CL_MASK			0x74
+#define	REG_DDR3_MR0_CL_OFFS			2
+#define	REG_DDR3_MR0_CL_HIGH_OFFS		3
+#define	CL_MASK					0xf
+
+#define	REG_DDR3_MR1_ADDR			0x15d4
+#define	REG_DDR3_MR1_CS_ADDR			0x1874
+#define REG_DDR3_MR1_RTT_MASK			0xfffffdbb
+#define REG_DDR3_MR1_DLL_ENA_OFFS		0
+#define REG_DDR3_MR1_RTT_DISABLED		0x0
+#define REG_DDR3_MR1_RTT_RZQ2			0x40
+#define REG_DDR3_MR1_RTT_RZQ4			0x2
+#define REG_DDR3_MR1_RTT_RZQ6			0x42
+#define REG_DDR3_MR1_RTT_RZQ8			0x202
+#define REG_DDR3_MR1_RTT_RZQ12			0x4
+/* WL-disabled, OB-enabled */
+#define REG_DDR3_MR1_OUTBUF_WL_MASK		0xffffef7f
+/* Output Buffer Disabled */
+#define REG_DDR3_MR1_OUTBUF_DIS_OFFS		12
+#define REG_DDR3_MR1_WL_ENA_OFFS		7
+#define REG_DDR3_MR1_WL_ENA			0x80	/* WL Enabled */
+#define REG_DDR3_MR1_ODT_MASK			0xfffffdbb
+
+#define	REG_DDR3_MR2_ADDR			0x15d8
+#define	REG_DDR3_MR2_CS_ADDR			0x1878
+#define	REG_DDR3_MR2_CWL_OFFS			3
+#define	REG_DDR3_MR2_CWL_MASK			0x7
+#define REG_DDR3_MR2_ODT_MASK			0xfffff9ff
+#define	REG_DDR3_MR3_ADDR			0x15dc
+#define	REG_DDR3_MR3_CS_ADDR			0x187c
+
+#define REG_DDR3_RANK_CTRL_ADDR			0x15e0
+#define REG_DDR3_RANK_CTRL_CS_ENA_MASK		0xf
+#define REG_DDR3_RANK_CTRL_MIRROR_OFFS		4
+
+#define REG_ZQC_CONF_ADDR			0x15e4
+
+#define REG_DRAM_PHY_CONFIG_ADDR		0x15ec
+#define REG_DRAM_PHY_CONFIG_MASK		0x3fffffff
+
+#define REG_ODPG_CNTRL_ADDR			0x1600
+#define REG_ODPG_CNTRL_OFFS			21
+
+#define REG_PHY_LOCK_MASK_ADDR			0x1670
+#define REG_PHY_LOCK_MASK_MASK			0xfffff000
+
+#define REG_PHY_LOCK_STATUS_ADDR		0x1674
+#define REG_PHY_LOCK_STATUS_LOCK_OFFS		9
+#define REG_PHY_LOCK_STATUS_LOCK_MASK		0xfff
+#define REG_PHY_LOCK_APLL_ADLL_STATUS_MASK	0x7ff
+
+#define REG_PHY_REGISTRY_FILE_ACCESS_ADDR	0x16a0
+#define REG_PHY_REGISTRY_FILE_ACCESS_OP_WR	0xc0000000
+#define REG_PHY_REGISTRY_FILE_ACCESS_OP_RD	0x80000000
+#define REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE	0x80000000
+#define REG_PHY_BC_OFFS				27
+#define REG_PHY_CNTRL_OFFS			26
+#define REG_PHY_CS_OFFS				16
+#define REG_PHY_DQS_REF_DLY_OFFS		10
+#define REG_PHY_PHASE_OFFS			8
+#define REG_PHY_PUP_OFFS			22
+
+#define REG_TRAINING_WL_ADDR			0x16ac
+#define REG_TRAINING_WL_CS_MASK			0xfffffffc
+#define REG_TRAINING_WL_UPD_OFFS		2
+#define REG_TRAINING_WL_CS_DONE_OFFS		3
+#define REG_TRAINING_WL_RATIO_MASK		0xffffff0f
+#define REG_TRAINING_WL_1TO1			0x50
+#define REG_TRAINING_WL_2TO1			0x10
+#define REG_TRAINING_WL_DELAYEXP_MASK		0x20000000
+#define REG_TRAINING_WL_RESULTS_MASK		0x000001ff
+#define REG_TRAINING_WL_RESULTS_OFFS		20
+
+#define REG_REGISTERED_DRAM_CTRL_ADDR		0x16d0
+#define REG_REGISTERED_DRAM_CTRL_SR_FLOAT_OFFS	15
+#define REG_REGISTERED_DRAM_CTRL_PARITY_MASK	0x3f
+
+/* DLB */
+#define REG_STATIC_DRAM_DLB_CONTROL		0x1700
+#define DLB_BUS_OPTIMIZATION_WEIGHTS_REG	0x1704
+#define DLB_AGING_REGISTER			0x1708
+#define DLB_EVICTION_CONTROL_REG		0x170c
+#define DLB_EVICTION_TIMERS_REGISTER_REG	0x1710
+#define DLB_USER_COMMAND_REG			0x1714
+#define DLB_BUS_WEIGHTS_DIFF_CS			0x1770
+#define DLB_BUS_WEIGHTS_DIFF_BG			0x1774
+#define DLB_BUS_WEIGHTS_SAME_BG			0x1778
+#define DLB_BUS_WEIGHTS_RD_WR			0x177c
+#define DLB_BUS_WEIGHTS_ATTR_SYS_PRIO		0x1780
+#define DLB_MAIN_QUEUE_MAP			0x1784
+#define DLB_LINE_SPLIT				0x1788
+
+#define DLB_ENABLE				0x1
+#define DLB_WRITE_COALESING			(0x1 << 2)
+#define DLB_AXI_PREFETCH_EN			(0x1 << 3)
+#define DLB_MBUS_PREFETCH_EN			(0x1 << 4)
+#define PREFETCH_N_LN_SZ_TR			(0x1 << 6)
+#define DLB_INTERJECTION_ENABLE			(0x1 << 3)
+
+/* CPU */
+#define REG_BOOTROM_ROUTINE_ADDR		0x182d0
+#define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS	12
+
+#define REG_DRAM_INIT_CTRL_STATUS_ADDR		0x18488
+#define REG_DRAM_INIT_CTRL_TRN_CLK_OFFS		16
+#define REG_CPU_DIV_CLK_CTRL_0_NEW_RATIO	0x000200ff
+#define REG_DRAM_INIT_CTRL_STATUS_2_ADDR	0x1488
+
+#define REG_CPU_DIV_CLK_CTRL_0_ADDR		0x18700
+
+#define REG_CPU_DIV_CLK_CTRL_1_ADDR		0x18704
+#define REG_CPU_DIV_CLK_CTRL_2_ADDR		0x18708
+
+#define REG_CPU_DIV_CLK_CTRL_3_ADDR		0x1870c
+#define REG_CPU_DIV_CLK_CTRL_3_FREQ_MASK	0xffffc0ff
+#define REG_CPU_DIV_CLK_CTRL_3_FREQ_OFFS	8
+
+#define REG_CPU_DIV_CLK_CTRL_4_ADDR		0x18710
+
+#define REG_CPU_DIV_CLK_STATUS_0_ADDR		0x18718
+#define REG_CPU_DIV_CLK_ALL_STABLE_OFFS		8
+
+#define REG_CPU_PLL_CTRL_0_ADDR			0x1871c
+#define REG_CPU_PLL_STATUS_0_ADDR		0x18724
+#define REG_CORE_DIV_CLK_CTRL_ADDR		0x18740
+#define REG_CORE_DIV_CLK_STATUS_ADDR		0x18744
+#define REG_DDRPHY_APLL_CTRL_ADDR		0x18780
+
+#define REG_DDRPHY_APLL_CTRL_2_ADDR		0x18784
+#define REG_SFABRIC_CLK_CTRL_ADDR		0x20858
+#define REG_SFABRIC_CLK_CTRL_SMPL_OFFS		8
+
+/* DRAM Windows */
+#define REG_XBAR_WIN_19_CTRL_ADDR		0x200e8
+#define REG_XBAR_WIN_4_CTRL_ADDR		0x20040
+#define REG_XBAR_WIN_4_BASE_ADDR		0x20044
+#define REG_XBAR_WIN_4_REMAP_ADDR		0x20048
+#define REG_FASTPATH_WIN_0_CTRL_ADDR		0x20184
+#define REG_XBAR_WIN_7_REMAP_ADDR               0x20078
+
+/* SRAM */
+#define REG_CDI_CONFIG_ADDR			0x20220
+#define REG_SRAM_WINDOW_0_ADDR			0x20240
+#define REG_SRAM_WINDOW_0_ENA_OFFS		0
+#define REG_SRAM_WINDOW_1_ADDR			0x20244
+#define REG_SRAM_L2_ENA_ADDR			0x8500
+#define REG_SRAM_CLEAN_BY_WAY_ADDR		0x87bc
+
+/* Timers */
+#define REG_TIMERS_CTRL_ADDR			0x20300
+#define REG_TIMERS_EVENTS_ADDR			0x20304
+#define REG_TIMER0_VALUE_ADDR			0x20314
+#define REG_TIMER1_VALUE_ADDR			0x2031c
+#define REG_TIMER0_ENABLE_MASK			0x1
+
+#define MV_BOARD_REFCLK_25MHZ			25000000
+#define CNTMR_RELOAD_REG(tmr)	(REG_TIMERS_CTRL_ADDR  + 0x10 + (tmr * 8))
+#define CNTMR_VAL_REG(tmr)	(REG_TIMERS_CTRL_ADDR  + 0x14 + (tmr * 8))
+#define CNTMR_CTRL_REG(tmr)	(REG_TIMERS_CTRL_ADDR)
+#define CTCR_ARM_TIMER_EN_OFFS(timer)	(timer * 2)
+#define CTCR_ARM_TIMER_EN_MASK(timer)	(1 << CTCR_ARM_TIMER_EN_OFFS(timer))
+#define CTCR_ARM_TIMER_EN(timer)	(1 << CTCR_ARM_TIMER_EN_OFFS(timer))
+
+#define CTCR_ARM_TIMER_AUTO_OFFS(timer)	(1 + (timer * 2))
+#define CTCR_ARM_TIMER_AUTO_MASK(timer)	(1 << CTCR_ARM_TIMER_EN_OFFS(timer))
+#define CTCR_ARM_TIMER_AUTO_EN(timer)	(1 << CTCR_ARM_TIMER_AUTO_OFFS(timer))
+
+/* PMU */
+#define REG_PMU_I_F_CTRL_ADDR			0x1c090
+#define REG_PMU_DUNIT_BLK_OFFS			16
+#define REG_PMU_DUNIT_RFRS_OFFS			20
+#define REG_PMU_DUNIT_ACK_OFFS			24
+
+/* MBUS */
+#define MBUS_UNITS_PRIORITY_CONTROL_REG		(MBUS_REGS_OFFSET + 0x420)
+#define FABRIC_UNITS_PRIORITY_CONTROL_REG	(MBUS_REGS_OFFSET + 0x424)
+#define MBUS_UNITS_PREFETCH_CONTROL_REG		(MBUS_REGS_OFFSET + 0x428)
+#define FABRIC_UNITS_PREFETCH_CONTROL_REG	(MBUS_REGS_OFFSET + 0x42c)
+
+#define REG_PM_STAT_MASK_ADDR			0x2210c
+#define REG_PM_STAT_MASK_CPU0_IDLE_MASK_OFFS	16
+
+#define REG_PM_EVENT_STAT_MASK_ADDR		0x22120
+#define REG_PM_EVENT_STAT_MASK_DFS_DONE_OFFS	17
+
+#define REG_PM_CTRL_CONFIG_ADDR			0x22104
+#define REG_PM_CTRL_CONFIG_DFS_REQ_OFFS		18
+
+#define REG_FABRIC_LOCAL_IRQ_MASK_ADDR		0x218c4
+#define REG_FABRIC_LOCAL_IRQ_PMU_MASK_OFFS	18
+
+/* Controller revision info */
+#define PCI_CLASS_CODE_AND_REVISION_ID		0x008
+#define PCCRIR_REVID_OFFS			0	/* Revision ID */
+#define PCCRIR_REVID_MASK			(0xff << PCCRIR_REVID_OFFS)
+
+/* Power Management Clock Gating Control Register */
+#define MV_PEX_IF_REGS_OFFSET(pex_if)				\
+	(pex_if < 8 ? (0x40000 + ((pex_if) / 4) * 0x40000 +	\
+		       ((pex_if) % 4) * 0x4000) :		\
+	 (0x42000 + ((pex_if) % 8) * 0x40000))
+#define PEX_IF_REGS_BASE(unit)			(MV_PEX_IF_REGS_OFFSET(unit))
+#define POWER_MNG_CTRL_REG			0x18220
+#define PEX_DEVICE_AND_VENDOR_ID		0x000
+#define PEX_CFG_DIRECT_ACCESS(if, reg)	(PEX_IF_REGS_BASE(if) + (reg))
+#define PMC_PEXSTOPCLOCK_OFFS(p)	((p) < 8 ? (5 + (p)) : (18 + (p)))
+#define PMC_PEXSTOPCLOCK_MASK(p)	(1 << PMC_PEXSTOPCLOCK_OFFS(p))
+#define PMC_PEXSTOPCLOCK_EN(p)		(1 << PMC_PEXSTOPCLOCK_OFFS(p))
+#define PMC_PEXSTOPCLOCK_STOP(p)	(0 << PMC_PEXSTOPCLOCK_OFFS(p))
+
+/* TWSI */
+#define TWSI_DATA_ADDR_MASK		0x7
+#define TWSI_DATA_ADDR_OFFS		1
+
+/* General */
+#define MAX_CS				4
+
+/* Frequencies */
+#define FAB_OPT				21
+#define CLK_CPU				12
+#define CLK_VCO				(2 * CLK_CPU)
+#define CLK_DDR				12
+
+/* CPU Frequencies: */
+#define CLK_CPU_1000			0
+#define CLK_CPU_1066			1
+#define CLK_CPU_1200			2
+#define CLK_CPU_1333			3
+#define CLK_CPU_1500			4
+#define CLK_CPU_1666			5
+#define CLK_CPU_1800			6
+#define CLK_CPU_2000			7
+#define CLK_CPU_600			8
+#define CLK_CPU_667			9
+#define CLK_CPU_800			0xa
+
+/* Extra Cpu Frequencies: */
+#define CLK_CPU_1600			11
+#define CLK_CPU_2133			12
+#define CLK_CPU_2200			13
+#define CLK_CPU_2400			14
+
+#define SAR1_CPU_CORE_MASK		0x00000018
+#define SAR1_CPU_CORE_OFFSET		3
+
+#endif /* _DDR3_HWS_HW_TRAINING_DEF_H */

drivers/ddr/marvell/a38x/ddr3_hws_sil_training.h

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _DDR3_HWS_SIL_TRAINING_H
+#define _DDR3_HWS_SIL_TRAINING_H
+
+#include "ddr3_training_ip.h"
+#include "ddr3_training_ip_prv_if.h"
+
+int ddr3_silicon_pre_config(void);
+int ddr3_silicon_init(void);
+int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq);
+
+#endif /* _DDR3_HWS_SIL_TRAINING_H */

drivers/ddr/marvell/a38x/ddr3_init.h

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _DDR3_INIT_H
+#define _DDR3_INIT_H
+
+#if defined(CONFIG_ARMADA_38X)
+#include "ddr3_a38x.h"
+#include "ddr3_a38x_mc_static.h"
+#include "ddr3_a38x_topology.h"
+#endif
+#include "ddr3_hws_hw_training.h"
+#include "ddr3_hws_sil_training.h"
+#include "ddr3_logging_def.h"
+#include "ddr3_training_hw_algo.h"
+#include "ddr3_training_ip.h"
+#include "ddr3_training_ip_centralization.h"
+#include "ddr3_training_ip_engine.h"
+#include "ddr3_training_ip_flow.h"
+#include "ddr3_training_ip_pbs.h"
+#include "ddr3_training_ip_prv_if.h"
+#include "ddr3_training_ip_static.h"
+#include "ddr3_training_leveling.h"
+#include "xor.h"
+
+/*
+ * MV_DEBUG_INIT need to be defines, otherwise the output of the
+ * DDR2 training code is not complete and misleading
+ */
+#define MV_DEBUG_INIT
+
+#define BIT(x)				(1 << (x))
+
+#ifdef MV_DEBUG_INIT
+#define DEBUG_INIT_S(s)			puts(s)
+#define DEBUG_INIT_D(d, l)		printf("%x", d)
+#define DEBUG_INIT_D_10(d, l)		printf("%d", d)
+#else
+#define DEBUG_INIT_S(s)
+#define DEBUG_INIT_D(d, l)
+#define DEBUG_INIT_D_10(d, l)
+#endif
+
+#ifdef MV_DEBUG_INIT_FULL
+#define DEBUG_INIT_FULL_S(s)		puts(s)
+#define DEBUG_INIT_FULL_D(d, l)		printf("%x", d)
+#define DEBUG_INIT_FULL_D_10(d, l)	printf("%d", d)
+#define DEBUG_WR_REG(reg, val) \
+	{ DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
+	  DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
+#define DEBUG_RD_REG(reg, val) \
+	{ DEBUG_INIT_S("Read  Reg: 0x"); DEBUG_INIT_D((reg), 8); \
+	  DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
+#else
+#define DEBUG_INIT_FULL_S(s)
+#define DEBUG_INIT_FULL_D(d, l)
+#define DEBUG_INIT_FULL_D_10(d, l)
+#define DEBUG_WR_REG(reg, val)
+#define DEBUG_RD_REG(reg, val)
+#endif
+
+#define DEBUG_INIT_FULL_C(s, d, l)			\
+	{ DEBUG_INIT_FULL_S(s);				\
+	  DEBUG_INIT_FULL_D(d, l);			\
+	  DEBUG_INIT_FULL_S("\n"); }
+#define DEBUG_INIT_C(s, d, l) \
+	{ DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
+
+/*
+ * Debug (Enable/Disable modules) and Error report
+ */
+
+#ifdef BASIC_DEBUG
+#define MV_DEBUG_WL
+#define MV_DEBUG_RL
+#define MV_DEBUG_DQS_RESULTS
+#endif
+
+#ifdef FULL_DEBUG
+#define MV_DEBUG_WL
+#define MV_DEBUG_RL
+#define MV_DEBUG_DQS
+
+#define MV_DEBUG_PBS
+#define MV_DEBUG_DFS
+#define MV_DEBUG_MAIN_FULL
+#define MV_DEBUG_DFS_FULL
+#define MV_DEBUG_DQS_FULL
+#define MV_DEBUG_RL_FULL
+#define MV_DEBUG_WL_FULL
+#endif
+
+#if defined(CONFIG_ARMADA_38X)
+#include "ddr3_a38x.h"
+#include "ddr3_a38x_topology.h"
+#endif
+
+/* The following is a list of Marvell status */
+#define MV_ERROR	(-1)
+#define MV_OK		(0x00)	/* Operation succeeded                   */
+#define MV_FAIL		(0x01)	/* Operation failed                      */
+#define MV_BAD_VALUE	(0x02)	/* Illegal value (general)               */
+#define MV_OUT_OF_RANGE	(0x03)	/* The value is out of range             */
+#define MV_BAD_PARAM	(0x04)	/* Illegal parameter in function called  */
+#define MV_BAD_PTR	(0x05)	/* Illegal pointer value                 */
+#define MV_BAD_SIZE	(0x06)	/* Illegal size                          */
+#define MV_BAD_STATE	(0x07)	/* Illegal state of state machine        */
+#define MV_SET_ERROR	(0x08)	/* Set operation failed                  */
+#define MV_GET_ERROR	(0x09)	/* Get operation failed                  */
+#define MV_CREATE_ERROR	(0x0a)	/* Fail while creating an item           */
+#define MV_NOT_FOUND	(0x0b)	/* Item not found                        */
+#define MV_NO_MORE	(0x0c)	/* No more items found                   */
+#define MV_NO_SUCH	(0x0d)	/* No such item                          */
+#define MV_TIMEOUT	(0x0e)	/* Time Out                              */
+#define MV_NO_CHANGE	(0x0f)	/* Parameter(s) is already in this value */
+#define MV_NOT_SUPPORTED (0x10)	/* This request is not support           */
+#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
+#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized          */
+#define MV_NO_RESOURCE	(0x13)	/* Resource not available (memory ...)   */
+#define MV_FULL		(0x14)	/* Item is full (Queue or table etc...)  */
+#define MV_EMPTY	(0x15)	/* Item is empty (Queue or table etc...) */
+#define MV_INIT_ERROR	(0x16)	/* Error occured while INIT process      */
+#define MV_HW_ERROR	(0x17)	/* Hardware error                        */
+#define MV_TX_ERROR	(0x18)	/* Transmit operation not succeeded      */
+#define MV_RX_ERROR	(0x19)	/* Recieve operation not succeeded       */
+#define MV_NOT_READY	(0x1a)	/* The other side is not ready yet       */
+#define MV_ALREADY_EXIST (0x1b)	/* Tried to create existing item         */
+#define MV_OUT_OF_CPU_MEM   (0x1c) /* Cpu memory allocation failed.      */
+#define MV_NOT_STARTED	(0x1d)	/* Not started yet                       */
+#define MV_BUSY		(0x1e)	/* Item is busy.                         */
+#define MV_TERMINATE	(0x1f)	/* Item terminates it's work.            */
+#define MV_NOT_ALIGNED	(0x20)	/* Wrong alignment                       */
+#define MV_NOT_ALLOWED	(0x21)	/* Operation NOT allowed                 */
+#define MV_WRITE_PROTECT (0x22)	/* Write protected                       */
+#define MV_INVALID	(int)(-1)
+
+/* For checking function return values */
+#define CHECK_STATUS(orig_func)		\
+	{				\
+		int status;		\
+		status = orig_func;	\
+		if (MV_OK != status)	\
+			return status;	\
+	}
+
+enum log_level  {
+	MV_LOG_LEVEL_0,
+	MV_LOG_LEVEL_1,
+	MV_LOG_LEVEL_2,
+	MV_LOG_LEVEL_3
+};
+
+/* Globals */
+extern u8 debug_training;
+extern u8 is_reg_dump;
+extern u8 generic_init_controller;
+extern u32 freq_val[];
+extern u32 is_pll_old;
+extern struct cl_val_per_freq cas_latency_table[];
+extern struct pattern_info pattern_table[];
+extern struct cl_val_per_freq cas_write_latency_table[];
+extern u8 debug_training;
+extern u8 debug_centralization, debug_training_ip, debug_training_bist,
+	debug_pbs, debug_training_static, debug_leveling;
+extern u32 pipe_multicast_mask;
+extern struct hws_tip_config_func_db config_func_info[];
+extern u8 cs_mask_reg[];
+extern u8 twr_mask_table[];
+extern u8 cl_mask_table[];
+extern u8 cwl_mask_table[];
+extern u16 rfc_table[];
+extern u32 speed_bin_table_t_rc[];
+extern u32 speed_bin_table_t_rcd_t_rp[];
+extern u32 ck_delay, ck_delay_16;
+
+extern u32 g_zpri_data;
+extern u32 g_znri_data;
+extern u32 g_zpri_ctrl;
+extern u32 g_znri_ctrl;
+extern u32 g_zpodt_data;
+extern u32 g_znodt_data;
+extern u32 g_zpodt_ctrl;
+extern u32 g_znodt_ctrl;
+extern u32 g_dic;
+extern u32 g_odt_config;
+extern u32 g_rtt_nom;
+
+extern u8 debug_training_access;
+extern u8 debug_training_a38x;
+extern u32 first_active_if;
+extern enum hws_ddr_freq init_freq;
+extern u32 delay_enable, ck_delay, ck_delay_16, ca_delay;
+extern u32 mask_tune_func;
+extern u32 rl_version;
+extern int rl_mid_freq_wa;
+extern u8 calibration_update_control; /* 2 external only, 1 is internal only */
+extern enum hws_ddr_freq medium_freq;
+
+extern u32 ck_delay, ck_delay_16;
+extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
+extern u32 first_active_if;
+extern u32 mask_tune_func;
+extern u32 freq_val[];
+extern enum hws_ddr_freq init_freq;
+extern enum hws_ddr_freq low_freq;
+extern enum hws_ddr_freq medium_freq;
+extern u8 generic_init_controller;
+extern enum auto_tune_stage training_stage;
+extern u32 is_pll_before_init;
+extern u32 is_adll_calib_before_init;
+extern u32 is_dfs_in_init;
+extern int wl_debug_delay;
+extern u32 silicon_delay[HWS_MAX_DEVICE_NUM];
+extern u32 p_finger;
+extern u32 n_finger;
+extern u32 freq_val[DDR_FREQ_LIMIT];
+extern u32 start_pattern, end_pattern;
+extern u32 phy_reg0_val;
+extern u32 phy_reg1_val;
+extern u32 phy_reg2_val;
+extern u32 phy_reg3_val;
+extern enum hws_pattern sweep_pattern;
+extern enum hws_pattern pbs_pattern;
+extern u8 is_rzq6;
+extern u32 znri_data_phy_val;
+extern u32 zpri_data_phy_val;
+extern u32 znri_ctrl_phy_val;
+extern u32 zpri_ctrl_phy_val;
+extern u8 debug_training_access;
+extern u32 finger_test, p_finger_start, p_finger_end, n_finger_start,
+	n_finger_end, p_finger_step, n_finger_step;
+extern u32 mode2_t;
+extern u32 xsb_validate_type;
+extern u32 xsb_validation_base_address;
+extern u32 odt_additional;
+extern u32 debug_mode;
+extern u32 delay_enable;
+extern u32 ca_delay;
+extern u32 debug_dunit;
+extern u32 clamp_tbl[];
+extern u32 freq_mask[HWS_MAX_DEVICE_NUM][DDR_FREQ_LIMIT];
+extern u32 start_pattern, end_pattern;
+
+extern u32 maxt_poll_tries;
+extern u32 is_bist_reset_bit;
+extern u8 debug_training_bist;
+
+extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
+extern u32 debug_mode;
+extern u32 effective_cs;
+extern int ddr3_tip_centr_skip_min_win_check;
+extern u32 *dq_map_table;
+extern enum auto_tune_stage training_stage;
+extern u8 debug_centralization;
+
+extern u32 delay_enable;
+extern u32 start_pattern, end_pattern;
+extern u32 freq_val[DDR_FREQ_LIMIT];
+extern u8 debug_training_hw_alg;
+extern enum auto_tune_stage training_stage;
+
+extern u8 debug_training_ip;
+extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
+extern enum auto_tune_stage training_stage;
+extern u32 effective_cs;
+
+extern u8 debug_leveling;
+extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
+extern enum auto_tune_stage training_stage;
+extern u32 rl_version;
+extern struct cl_val_per_freq cas_latency_table[];
+extern u32 start_xsb_offset;
+extern u32 debug_mode;
+extern u32 odt_config;
+extern u32 effective_cs;
+extern u32 phy_reg1_val;
+
+extern u8 debug_pbs;
+extern u32 effective_cs;
+extern u16 mask_results_dq_reg_map[];
+extern enum hws_ddr_freq medium_freq;
+extern u32 freq_val[];
+extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
+extern enum auto_tune_stage training_stage;
+extern u32 debug_mode;
+extern u32 *dq_map_table;
+
+extern u32 vref;
+extern struct cl_val_per_freq cas_latency_table[];
+extern u32 target_freq;
+extern struct hws_tip_config_func_db config_func_info[HWS_MAX_DEVICE_NUM];
+extern u32 clamp_tbl[];
+extern u32 init_freq;
+/* list of allowed frequency listed in order of enum hws_ddr_freq */
+extern u32 freq_val[];
+extern u8 debug_training_static;
+extern u32 first_active_if;
+
+/* Prototypes */
+int ddr3_tip_enable_init_sequence(u32 dev_num);
+
+int ddr3_tip_init_a38x(u32 dev_num, u32 board_id);
+
+int ddr3_hws_hw_training(void);
+int ddr3_silicon_pre_init(void);
+int ddr3_silicon_post_init(void);
+int ddr3_post_run_alg(void);
+int ddr3_if_ecc_enabled(void);
+void ddr3_new_tip_ecc_scrub(void);
+
+void ddr3_print_version(void);
+void ddr3_new_tip_dlb_config(void);
+struct hws_topology_map *ddr3_get_topology_map(void);
+
+int ddr3_if_ecc_enabled(void);
+int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
+int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
+int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq);
+int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq,
+				  struct hws_tip_freq_config_info
+				  *freq_config_info);
+int ddr3_a38x_update_topology_map(u32 dev_num,
+				  struct hws_topology_map *topology_map);
+int ddr3_tip_a38x_get_init_freq(int dev_num, enum hws_ddr_freq *freq);
+int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq);
+int ddr3_tip_a38x_if_read(u8 dev_num, enum hws_access_type interface_access,
+			  u32 if_id, u32 reg_addr, u32 *data, u32 mask);
+int ddr3_tip_a38x_if_write(u8 dev_num, enum hws_access_type interface_access,
+			   u32 if_id, u32 reg_addr, u32 data, u32 mask);
+int ddr3_tip_a38x_get_device_info(u8 dev_num,
+				  struct ddr3_device_info *info_ptr);
+
+int ddr3_tip_init_a38x(u32 dev_num, u32 board_id);
+
+int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
+int ddr3_tip_restore_dunit_regs(u32 dev_num);
+void print_topology(struct hws_topology_map *topology_db);
+
+u32 mv_board_id_get(void);
+
+int ddr3_load_topology_map(void);
+int ddr3_tip_init_specific_reg_config(u32 dev_num,
+				      struct reg_data *reg_config_arr);
+u32 ddr3_tip_get_init_freq(void);
+void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level);
+int ddr3_tip_tune_training_params(u32 dev_num,
+				  struct tune_train_params *params);
+void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
+int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena);
+void ddr3_fast_path_static_cs_size_config(u32 cs_ena);
+u32 ddr3_get_device_width(u32 cs);
+u32 mv_board_id_index_get(u32 board_id);
+u32 mv_board_id_get(void);
+u32 ddr3_get_bus_width(void);
+void ddr3_set_log_level(u32 n_log_level);
+int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size);
+
+int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr);
+
+int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
+int ddr3_tip_clean_pbs_result(u32 dev_num, enum pbs_dir pbs_mode);
+
+int ddr3_tip_static_round_trip_arr_build(u32 dev_num,
+					 struct trip_delay_element *table_ptr,
+					 int is_wl, u32 *round_trip_delay_arr);
+
+u32 hws_ddr3_tip_max_cs_get(void);
+
+/*
+ * Accessor functions for the registers
+ */
+static inline void reg_write(u32 addr, u32 val)
+{
+	writel(val, INTER_REGS_BASE + addr);
+}
+
+static inline u32 reg_read(u32 addr)
+{
+	return readl(INTER_REGS_BASE + addr);
+}
+
+static inline void reg_bit_set(u32 addr, u32 mask)
+{
+	setbits_le32(INTER_REGS_BASE + addr, mask);
+}
+
+static inline void reg_bit_clr(u32 addr, u32 mask)
+{
+	clrbits_le32(INTER_REGS_BASE + addr, mask);
+}
+
+#endif /* _DDR3_INIT_H */

drivers/ddr/marvell/a38x/ddr3_logging_def.h

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _DDR3_LOGGING_CONFIG_H
+#define _DDR3_LOGGING_CONFIG_H
+
+#ifdef SILENT_LIB
+#define DEBUG_TRAINING_BIST_ENGINE(level, s)
+#define DEBUG_TRAINING_IP(level, s)
+#define DEBUG_CENTRALIZATION_ENGINE(level, s)
+#define DEBUG_TRAINING_HW_ALG(level, s)
+#define DEBUG_TRAINING_IP_ENGINE(level, s)
+#define DEBUG_LEVELING(level, s)
+#define DEBUG_PBS_ENGINE(level, s)
+#define DEBUG_TRAINING_STATIC_IP(level, s)
+#define DEBUG_TRAINING_ACCESS(level, s)
+#else
+#ifdef LIB_FUNCTIONAL_DEBUG_ONLY
+#define DEBUG_TRAINING_BIST_ENGINE(level, s)
+#define DEBUG_TRAINING_IP_ENGINE(level, s)
+#define DEBUG_TRAINING_IP(level, s)		\
+	if (level >= debug_training)		\
+		printf s
+#define DEBUG_CENTRALIZATION_ENGINE(level, s)	\
+	if (level >= debug_centralization)	\
+		printf s
+#define DEBUG_TRAINING_HW_ALG(level, s)		\
+	if (level >= debug_training_hw_alg)	\
+		printf s
+#define DEBUG_LEVELING(level, s)		\
+	if (level >= debug_leveling)		\
+		printf s
+#define DEBUG_PBS_ENGINE(level, s)		\
+	if (level >= debug_pbs)			\
+		printf s
+#define DEBUG_TRAINING_STATIC_IP(level, s)	\
+	if (level >= debug_training_static)	\
+		printf s
+#define DEBUG_TRAINING_ACCESS(level, s)		\
+	if (level >= debug_training_access)	\
+		printf s
+#else
+#define DEBUG_TRAINING_BIST_ENGINE(level, s)	\
+	if (level >= debug_training_bist)	\
+		printf s
+
+#define DEBUG_TRAINING_IP_ENGINE(level, s)	\
+	if (level >= debug_training_ip)		\
+		printf s
+#define DEBUG_TRAINING_IP(level, s)		\
+	if (level >= debug_training)		\
+		printf s
+#define DEBUG_CENTRALIZATION_ENGINE(level, s)	\
+	if (level >= debug_centralization)	\
+		printf s
+#define DEBUG_TRAINING_HW_ALG(level, s)		\
+	if (level >= debug_training_hw_alg)	\
+		printf s
+#define DEBUG_LEVELING(level, s)		\
+	if (level >= debug_leveling)		\
+		printf s
+#define DEBUG_PBS_ENGINE(level, s)		\
+	if (level >= debug_pbs)			\
+		printf s
+#define DEBUG_TRAINING_STATIC_IP(level, s)	\
+	if (level >= debug_training_static)	\
+		printf s
+#define DEBUG_TRAINING_ACCESS(level, s)		\
+	if (level >= debug_training_access)	\
+		printf s
+#endif
+#endif
+
+/* Logging defines */
+#define DEBUG_LEVEL_TRACE	1
+#define DEBUG_LEVEL_INFO	2
+#define DEBUG_LEVEL_ERROR	3
+
+enum ddr_lib_debug_block {
+	DEBUG_BLOCK_STATIC,
+	DEBUG_BLOCK_TRAINING_MAIN,
+	DEBUG_BLOCK_LEVELING,
+	DEBUG_BLOCK_CENTRALIZATION,
+	DEBUG_BLOCK_PBS,
+	DEBUG_BLOCK_IP,
+	DEBUG_BLOCK_BIST,
+	DEBUG_BLOCK_ALG,
+	DEBUG_BLOCK_DEVICE,
+	DEBUG_BLOCK_ACCESS,
+	DEBUG_STAGES_REG_DUMP,
+	/* All excluding IP and REG_DUMP, should be enabled separatelly */
+	DEBUG_BLOCK_ALL
+};
+
+int ddr3_tip_print_log(u32 dev_num, u32 mem_addr);
+int ddr3_tip_print_stability_log(u32 dev_num);
+
+#endif /* _DDR3_LOGGING_CONFIG_H */

drivers/ddr/marvell/a38x/ddr3_topology_def.h

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _DDR3_TOPOLOGY_DEF_H
+#define _DDR3_TOPOLOGY_DEF_H
+
+/* TOPOLOGY */
+
+enum hws_speed_bin {
+	SPEED_BIN_DDR_800D,
+	SPEED_BIN_DDR_800E,
+	SPEED_BIN_DDR_1066E,
+	SPEED_BIN_DDR_1066F,
+	SPEED_BIN_DDR_1066G,
+	SPEED_BIN_DDR_1333F,
+	SPEED_BIN_DDR_1333G,
+	SPEED_BIN_DDR_1333H,
+	SPEED_BIN_DDR_1333J,
+	SPEED_BIN_DDR_1600G,
+	SPEED_BIN_DDR_1600H,
+	SPEED_BIN_DDR_1600J,
+	SPEED_BIN_DDR_1600K,
+	SPEED_BIN_DDR_1866J,
+	SPEED_BIN_DDR_1866K,
+	SPEED_BIN_DDR_1866L,
+	SPEED_BIN_DDR_1866M,
+	SPEED_BIN_DDR_2133K,
+	SPEED_BIN_DDR_2133L,
+	SPEED_BIN_DDR_2133M,
+	SPEED_BIN_DDR_2133N,
+
+	SPEED_BIN_DDR_1333H_EXT,
+	SPEED_BIN_DDR_1600K_EXT,
+	SPEED_BIN_DDR_1866M_EXT
+};
+
+enum hws_ddr_freq {
+	DDR_FREQ_LOW_FREQ,
+	DDR_FREQ_400,
+	DDR_FREQ_533,
+	DDR_FREQ_667,
+	DDR_FREQ_800,
+	DDR_FREQ_933,
+	DDR_FREQ_1066,
+	DDR_FREQ_311,
+	DDR_FREQ_333,
+	DDR_FREQ_467,
+	DDR_FREQ_850,
+	DDR_FREQ_600,
+	DDR_FREQ_300,
+	DDR_FREQ_900,
+	DDR_FREQ_360,
+	DDR_FREQ_1000,
+	DDR_FREQ_LIMIT
+};
+
+enum speed_bin_table_elements {
+	SPEED_BIN_TRCD,
+	SPEED_BIN_TRP,
+	SPEED_BIN_TRAS,
+	SPEED_BIN_TRC,
+	SPEED_BIN_TRRD1K,
+	SPEED_BIN_TRRD2K,
+	SPEED_BIN_TPD,
+	SPEED_BIN_TFAW1K,
+	SPEED_BIN_TFAW2K,
+	SPEED_BIN_TWTR,
+	SPEED_BIN_TRTP,
+	SPEED_BIN_TWR,
+	SPEED_BIN_TMOD
+};
+
+#endif /* _DDR3_TOPOLOGY_DEF_H */

drivers/ddr/marvell/a38x/ddr3_training_hw_algo.h

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_HW_ALGO_H_
+#define _DDR3_TRAINING_HW_ALGO_H_
+
+int ddr3_tip_vref(u32 dev_num);
+int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id);
+int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap);
+
+#endif /* _DDR3_TRAINING_HW_ALGO_H_ */

drivers/ddr/marvell/a38x/ddr3_training_ip_bist.h

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_IP_BIST_H_
+#define _DDR3_TRAINING_IP_BIST_H_
+
+#include "ddr3_training_ip.h"
+
+enum hws_bist_operation {
+	BIST_STOP = 0,
+	BIST_START = 1
+};
+
+enum  hws_stress_jump {
+	STRESS_NONE = 0,
+	STRESS_ENABLE = 1
+};
+
+enum hws_pattern_duration {
+	DURATION_SINGLE = 0,
+	DURATION_STOP_AT_FAIL = 1,
+	DURATION_ADDRESS = 2,
+	DURATION_CONT = 4
+};
+
+struct bist_result {
+	u32 bist_error_cnt;
+	u32 bist_fail_low;
+	u32 bist_fail_high;
+	u32 bist_last_fail_addr;
+};
+
+int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
+			      struct bist_result *pst_bist_result);
+int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,
+			   enum hws_access_type access_type,
+			   u32 if_num, enum hws_dir direction,
+			   enum hws_stress_jump addr_stress_jump,
+			   enum hws_pattern_duration duration,
+			   enum hws_bist_operation oper_type,
+			   u32 offset, u32 cs_num, u32 pattern_addr_length);
+int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
+		      u32 cs_num);
+int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction,
+			    u32 mode);
+int ddr3_tip_print_regs(u32 dev_num);
+int ddr3_tip_reg_dump(u32 dev_num);
+int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type,
+		 u32 burst_length);
+
+#endif /* _DDR3_TRAINING_IP_BIST_H_ */

drivers/ddr/marvell/a38x/ddr3_training_ip_centralization.h

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_IP_CENTRALIZATION_H
+#define _DDR3_TRAINING_IP_CENTRALIZATION_H
+
+int ddr3_tip_centralization_tx(u32 dev_num);
+int ddr3_tip_centralization_rx(u32 dev_num);
+int ddr3_tip_print_centralization_result(u32 dev_num);
+int ddr3_tip_special_rx(u32 dev_num);
+
+#endif /* _DDR3_TRAINING_IP_CENTRALIZATION_H */

drivers/ddr/marvell/a38x/ddr3_training_ip_db.h

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_IP_DB_H_
+#define _DDR3_TRAINING_IP_DB_H_
+
+enum hws_pattern {
+	PATTERN_PBS1,
+	PATTERN_PBS2,
+	PATTERN_RL,
+	PATTERN_STATIC_PBS,
+	PATTERN_KILLER_DQ0,
+	PATTERN_KILLER_DQ1,
+	PATTERN_KILLER_DQ2,
+	PATTERN_KILLER_DQ3,
+	PATTERN_KILLER_DQ4,
+	PATTERN_KILLER_DQ5,
+	PATTERN_KILLER_DQ6,
+	PATTERN_KILLER_DQ7,
+	PATTERN_PBS3,
+	PATTERN_RL2,
+	PATTERN_TEST,
+	PATTERN_FULL_SSO0,
+	PATTERN_FULL_SSO1,
+	PATTERN_FULL_SSO2,
+	PATTERN_FULL_SSO3,
+	PATTERN_VREF,
+	PATTERN_LIMIT
+};
+
+#endif /* _DDR3_TRAINING_IP_DB_H_ */

drivers/ddr/marvell/a38x/ddr3_training_ip_pbs.h

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_IP_PBS_H_
+#define _DDR3_TRAINING_IP_PBS_H_
+
+enum {
+	EBA_CONFIG,
+	EEBA_CONFIG,
+	SBA_CONFIG
+};
+
+enum hws_training_load_op {
+	TRAINING_LOAD_OPERATION_UNLOAD,
+	TRAINING_LOAD_OPERATION_LOAD
+};
+
+enum hws_edge {
+	TRAINING_EDGE_1,
+	TRAINING_EDGE_2
+};
+
+enum hws_edge_search {
+	TRAINING_EDGE_MAX,
+	TRAINING_EDGE_MIN
+};
+
+enum pbs_dir {
+	PBS_TX_MODE = 0,
+	PBS_RX_MODE,
+	NUM_OF_PBS_MODES
+};
+
+int ddr3_tip_pbs_rx(u32 dev_num);
+int ddr3_tip_print_all_pbs_result(u32 dev_num);
+int ddr3_tip_pbs_tx(u32 dev_num);
+
+#endif /* _DDR3_TRAINING_IP_PBS_H_ */

drivers/ddr/marvell/a38x/ddr3_training_ip_static.h

+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_IP_STATIC_H_
+#define _DDR3_TRAINING_IP_STATIC_H_
+
+#include "ddr3_training_ip_def.h"
+#include "ddr3_training_ip.h"
+
+struct trip_delay_element {
+	u32 dqs_delay;		/* DQS delay (m_sec) */
+	u32 ck_delay;		/* CK Delay  (m_sec) */
+};
+
+struct hws_tip_static_config_info {
+	u32 silicon_delay;
+	struct trip_delay_element *package_trace_arr;
+	struct trip_delay_element *board_trace_arr;
+};
+
+int ddr3_tip_run_static_alg(u32 dev_num, enum hws_ddr_freq freq);
+int ddr3_tip_init_static_config_db(
+	u32 dev_num, struct hws_tip_static_config_info *static_config_info);
+int ddr3_tip_init_specific_reg_config(u32 dev_num,
+				      struct reg_data *reg_config_arr);
+int ddr3_tip_static_phy_init_controller(u32 dev_num);
+
+#endif /* _DDR3_TRAINING_IP_STATIC_H_ */