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  1. 12 7月, 2013 15 次提交
  3. 11 7月, 2013 1 次提交
  5. 10 7月, 2013 1 次提交
  7. 09 7月, 2013 1 次提交
  9. 05 7月, 2013 6 次提交
  11. 02 7月, 2013 4 次提交
    • A
      ARM: OMAP: GPIO: Fix valid range and enable usage of all GPIOs on OMAP5 · 87bd05d7
      由 Axel Lin 提交于 
      The omap_gpio driver is used by AM33XX, OMAP3/4, OMAP54XX and DRA7XX SoCs.
These SoCs have different gpio count but currently omap_gpio driver uses hard
coded 192 which is wrong.

This patch fixes this issue by:
1. Move define of OMAP_MAX_GPIO to all arch/arm/include/asm/arch-omap*/gpio.h.
2. Update gpio bank settings and enable GPIO modules 7 & 8 clocks for OMAP5.

Thanks for Lubomir Popov to provide valuable comments to fix this issue.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Tested-by: NLubomir Popov <lpopov@mm-sol.com>
Acked-by: NHeiko Schocher <hs@denx.de>
      87bd05d7
    • L
      ARM: OMAP4+: Fix MA detection during SDRAM_AUTO_DETECTION · e3f53104
      由 Lokesh Vutla 提交于 
      During SDRAM_AUTO_DETECTION MA is not configured.
For Soc's > OMAP4460 MA is present. So populating
MA for the same.

Tested on OMAP4430 PANDA, OMAP4460 PANDA.
Reported-by: NDan Murphy <dmurphy@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
      e3f53104
    • I
      am33xx: fix the ddr_cmdtctrl structure · 58c86c7d
      由 Ilya Ledvich 提交于 
      Fix the wrong mapping between the DDR I/O control registers on AM33XX
SoCs and the software representation in the SPL code.
The most recent public TRM defines the following DDR I/O control registers
offsets:
 * ddr_cmd0_ioctrl : offset 0x44E11404
 * ddr_cmd1_ioctrl : offset 0x44E11408
 * ddr_cmd2_ioctrl : offset 0x44E1140C
 * ddr_data0_ioctrl: offset 0x44E11440
 * ddr_data1_ioctrl: offset 0x44E11444

While the struct ddr_cmdtctrl has also some reserved bits in the beginning.
The struct is mapped to the address 0x44E11404. As a result "cm0ioctl" points
to the ddr_cmd1_ioctrl register, "cm1ioctl" to the ddr_cmd2_ioctrl and etc.
Registers ddr_cmd0_ioctrl and ddr_data0_ioctrl are never configured because
of this mapping mismatch.
Signed-off-by: NIlya Ledvich <ilya@compulab.co.il>
Reviewed-by: NPeter Korsgaard <jacmet@sunsite.dk>
      58c86c7d
    • M
      usb: omap: ulpi: fix ulpi transceiver access · b0857c45
      由 Michael Trimarchi 提交于 
      This patch fix the omap access to the transceiver
configuration registers using the ulpi bus. As reported by
the documentation the bit31 is used only to check if the
transaction is done or still running and the reading and
writing operation have different offset and have different
values. What we need to do at the end of a transaction is
leave the bus in done state. Anyway an error using the ulpi
omap register is not recoverable so any error give out the
usage of this interface.

Tested on a custom OMAP5430 board with a TUSB1210 ULPI PHY
on USBB1.
Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com>
Acked-by: NIgor Grinberg <grinberg@compulab.co.il>
Tested-by: NLubomir Popov <lpopov@mm-sol.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
      b0857c45
  13. 28 6月, 2013 6 次提交
  15. 26 6月, 2013 6 次提交