- 10 5月, 2017 40 次提交
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由 Álvaro Fernández Rojas 提交于
CFE checks CPU Thread in a different way (using register $22): mfc0 t1, C0_BCM_CONFIG, 3 # $22 li t2, CP0_CMT_TPID # (1 << 31) and t1, t2 bnez t1, 2f # if we are running on thread 1, skip init nop Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
Use uclass_first_device and uclass_next_device in order to avoid exceptions for drivers that aren't probed when cpu ops are requested. Improve code style and fix indentations. Fix incorrect line break when cpu info is not available. Remove unneeded brackets. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
It is based on linux/drivers/tty/serial/bcm63xx_uart.c Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
Avoid duplicating do_reset definition if SYSRESET is enabled for MIPS Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
Add a new sysreset driver based on linux/drivers/power/reset/syscon-reboot.c, which provides a generic driver for platforms that only require writing a mask to a regmap offset. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
Commit 740d5d34 added two new features but only one feature name, which results in NULL prints when device_id feature is selected. Before: HG556a # cpu detail -1: cpu@0 BCM6358A1 ID = 0, freq = 300 MHz: L1 cache, MMU, NULL Device ID 0x2a010 -1: cpu@1 BCM6358A1 ID = 1, freq = 300 MHz: L1 cache, MMU, NULL Device ID 0x2a010 After: HG556a # cpu detail -1: cpu@0 BCM6358A1 ID = 0, freq = 300 MHz: L1 cache, MMU, Device ID Device ID 0x2a010 -1: cpu@1 BCM6358A1 ID = 1, freq = 300 MHz: L1 cache, MMU, Device ID Device ID 0x2a010 Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Daniel Schwierzeck 提交于
All MIPS boards that support debug uart are calling debug_uart_init right at the beginning of board_early_init_f. Instead of doing that, let's provide a generic call to debug_uart_init right before the call to board_init_f if debug uart is enabled for boards without stack in SRAM. On the other hand, boards with stack in SRAM can call earlier (right before low level init). Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
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由 Álvaro Fernández Rojas 提交于
In order to add a generic MIPS debug_uart_init call right before the call to board_early_init_f, we need to remove all calls to debug_uart_init from every MIPS boards. WDR4300 doesn't provide a board_debug_uart_init and configures pinmux in board_early_init_f instead. Since I have no idead of what's the needed uart pinmux config, I copied the whole pinmux config to a new function that is called from board_early_init_f if CONFIG_DEBUG_UART_BOARD_INIT is not enabled. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
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由 Álvaro Fernández Rojas 提交于
In order to add a generic MIPS debug_uart_init call right before the call to board_early_init_f, we need to remove all calls to debug_uart_init from every MIPS boards. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
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由 Álvaro Fernández Rojas 提交于
In order to add a generic MIPS debug_uart_init call right before the call to board_early_init_f, we need to remove all calls to debug_uart_init from every MIPS boards. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
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由 Álvaro Fernández Rojas 提交于
This way we can see output about u-boot.elf being built or not. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Álvaro Fernández Rojas 提交于
Define PLATFORM_ELFFLAGS for MIPS in order to be able to generate u-boot.elf Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
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由 Álvaro Fernández Rojas 提交于
LD gives the following warning when trying to process u-boot-elf.o warning: cannot find entry symbol __start; defaulting to 0000000080010000 According to gnu-libc the entry symbol for mips is __start and not _start: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/mips/dl-machine.h;h=ed47513ccc1d23d23d32ee640053d2f351f3990b;hb=HEAD#l258Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Álvaro Fernández Rojas 提交于
This is needed in order to allow building it for other archs. Move relocation comment to a better place. Remove no longer needed dts FIXME. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Jean-Jacques Hiblot 提交于
Enable disk driver model for dra7xx_evm as dwc_ahci supports driver model. As a consequence we must also enable CONFIG_BLK and CONFIG_DM_USB. Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Dropped CONFIG_SPL_PHY=y in sandbox_spl to fix build error: Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Jean-Jacques Hiblot 提交于
Implement a sata driver for Synopsys DWC sata device based on U-boot driver model. Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Jean-Jacques Hiblot 提交于
This is needed to probe devices under that bus such as the SATA PHY. Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Jean-Jacques Hiblot 提交于
This phy is found on omap platforms with sata capabilities. Except for the part related to the DM and the PHY framework, the code is basically a copy paste from arch/arm/mach-omap2/pipe3-phy.c Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Jean-Jacques Hiblot 提交于
Those tests check: - the ability for a phy-user to get a phy based on its name or its index - the ability of a phy device (provider) to manage multiple ports - the ability to perform operations on the phy (init,deinit,on,off) - the behavior of the uclass when optional operations are not implemented Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Jean-Jacques Hiblot 提交于
The PHY framework provides a set of APIs to control a PHY. This API is derived from the linux version of the generic PHY framework. Currently the API supports init(), deinit(), power_on, power_off() and reset(). The framework provides a way to get a reference to a phy from the device-tree. Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Jean-Jacques Hiblot 提交于
The DM version of scsi_scan() is becoming a bit long, it can be split: scsi_scan() iterates over the IDs and LUNs and for each id/lun pair calls do_scsi_scan_one() to do the work of: - detecting an attached drive - creating the associated block device if a drive is found. Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
Because the introduction of the pinctrl and clk drivers and the device tree files, remove unneeded hard coded related code from the board file. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
Update the configuration files to support the device tree and driver model. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
Since the introduction of the pinctrl and clk drivers and the device tree files, remove unneeded hard coded related code from the board file. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
Update the configuration files to support the device tree and driver model. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
Since the introduction of the pinctrl and clk drivers and the device tree files, remove unneeded hard coded related code from the board file. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
Update the configuration files to support the device tree and driver model. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
Since the introduction of the pinctrl and clk drivers and the device tree files, remove unneeded hard coded related code from the board file. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
Update the configuration files to support the device tree and driver model. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Because the limitation of internal SRAM size, the SPL with driver model can't be supported, disable the SPL option. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
Since the introduction of the pinctrl and clk driver and the device tree files, remove unneeded related code from the board file. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
Update the configuration files to support the device tree and driver model. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Because the limitation of internal SRAM size, the SPL with driver model can't be supported, disable the SPL option. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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