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体验新版 GitCode,发现更多精彩内容 >>
提交
a2842129
编写于
5月 09, 2017
作者:
T
Tom Rini
浏览文件
操作
浏览文件
下载
差异文件
Merge
git://www.denx.de/git/u-boot-marvell
上级
e6ceaff1
e38f5fc8
变更
28
展开全部
隐藏空白更改
内联
并排
Showing
28 changed file
with
1247 addition
and
249 deletion
+1247
-249
arch/arm/dts/Makefile
arch/arm/dts/Makefile
+1
-0
arch/arm/dts/armada-385-amc.dts
arch/arm/dts/armada-385-amc.dts
+3
-0
arch/arm/dts/armada-7040-db-nand.dts
arch/arm/dts/armada-7040-db-nand.dts
+223
-0
arch/arm/dts/armada-7040-db.dts
arch/arm/dts/armada-7040-db.dts
+2
-1
arch/arm/dts/armada-8040-db.dts
arch/arm/dts/armada-8040-db.dts
+115
-107
arch/arm/dts/armada-8040-mcbin.dts
arch/arm/dts/armada-8040-mcbin.dts
+7
-7
arch/arm/dts/armada-cp110-master.dtsi
arch/arm/dts/armada-cp110-master.dtsi
+16
-2
arch/arm/dts/armada-cp110-slave.dtsi
arch/arm/dts/armada-cp110-slave.dtsi
+1
-1
arch/arm/mach-mvebu/arm64-common.c
arch/arm/mach-mvebu/arm64-common.c
+6
-0
arch/arm/mach-mvebu/armada8k/cpu.c
arch/arm/mach-mvebu/armada8k/cpu.c
+18
-0
arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c
arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c
+0
-2
arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
+2
-2
arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
+3
-3
arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c
arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c
+0
-1
cmd/mvebu/bubt.c
cmd/mvebu/bubt.c
+7
-6
configs/db-88f6820-amc_defconfig
configs/db-88f6820-amc_defconfig
+2
-0
configs/mvebu_db-88f7040-nand_defconfig
configs/mvebu_db-88f7040-nand_defconfig
+72
-0
drivers/mtd/nand/pxa3xx_nand.c
drivers/mtd/nand/pxa3xx_nand.c
+54
-8
drivers/net/mvpp2.c
drivers/net/mvpp2.c
+24
-0
drivers/pci/pcie_dw_mvebu.c
drivers/pci/pcie_dw_mvebu.c
+5
-5
drivers/phy/marvell/comphy.h
drivers/phy/marvell/comphy.h
+2
-1
drivers/phy/marvell/comphy_core.c
drivers/phy/marvell/comphy_core.c
+8
-8
drivers/phy/marvell/comphy_cp110.c
drivers/phy/marvell/comphy_cp110.c
+391
-58
drivers/phy/marvell/comphy_hpipe.h
drivers/phy/marvell/comphy_hpipe.h
+256
-21
drivers/phy/marvell/comphy_mux.c
drivers/phy/marvell/comphy_mux.c
+7
-0
include/configs/db-88f6820-amc.h
include/configs/db-88f6820-amc.h
+0
-7
include/configs/mvebu_armada-8k.h
include/configs/mvebu_armada-8k.h
+11
-0
include/dt-bindings/comphy/comphy_data.h
include/dt-bindings/comphy/comphy_data.h
+11
-9
未找到文件。
arch/arm/dts/Makefile
浏览文件 @
a2842129
...
...
@@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-388-gp.dtb
\
armada-385-amc.dtb
\
armada-7040-db.dtb
\
armada-7040-db-nand.dtb
\
armada-8040-db.dtb
\
armada-8040-mcbin.dtb
\
armada-xp-gp.dtb
\
...
...
arch/arm/dts/armada-385-amc.dts
浏览文件 @
a2842129
...
...
@@ -54,6 +54,7 @@
aliases
{
ethernet0
=
&
eth0
;
ethernet1
=
&
eth1
;
i2c0
=
&
i2c0
;
spi1
=
&
spi1
;
};
...
...
@@ -68,6 +69,8 @@
internal
-
regs
{
i2c
@
11000
{
clock
-
frequency
=
<
100000
>;
u
-
boot
,
i2c
-
slave
-
addr
=
<
0x0
>;
pinctrl
-
names
=
"default"
;
pinctrl
-
0
=
<&
i2c0_pins
>;
status
=
"okay"
;
...
...
arch/arm/dts/armada-7040-db-nand.dts
0 → 100644
浏览文件 @
a2842129
/*
*
Copyright
(
C
)
2017
Marvell
Technology
Group
Ltd
.
*
*
This
file
is
dual
-
licensed
:
you
can
use
it
either
under
the
terms
*
of
the
GPLv2
or
the
X11
license
,
at
your
option
.
Note
that
this
dual
*
licensing
only
applies
to
this
file
,
and
not
this
project
as
a
*
whole
.
*
*
a
)
This
library
is
free
software
;
you
can
redistribute
it
and
/
or
*
modify
it
under
the
terms
of
the
GNU
General
Public
License
as
*
published
by
the
Free
Software
Foundation
;
either
version
2
of
the
*
License
,
or
(
at
your
option
)
any
later
version
.
*
*
This
library
is
distributed
in
the
hope
that
it
will
be
useful
,
*
but
WITHOUT
ANY
WARRANTY
;
without
even
the
implied
warranty
of
*
MERCHANTABILITY
or
FITNESS
FOR
A
PARTICULAR
PURPOSE
.
See
the
*
GNU
General
Public
License
for
more
details
.
*
*
Or
,
alternatively
,
*
*
b
)
Permission
is
hereby
granted
,
free
of
charge
,
to
any
person
*
obtaining
a
copy
of
this
software
and
associated
documentation
*
files
(
the
"Software"
),
to
deal
in
the
Software
without
*
restriction
,
including
without
limitation
the
rights
to
use
,
*
copy
,
modify
,
merge
,
publish
,
distribute
,
sublicense
,
and
/
or
*
sell
copies
of
the
Software
,
and
to
permit
persons
to
whom
the
*
Software
is
furnished
to
do
so
,
subject
to
the
following
*
conditions
:
*
*
The
above
copyright
notice
and
this
permission
notice
shall
be
*
included
in
all
copies
or
substantial
portions
of
the
Software
.
*
*
THE
SOFTWARE
IS
PROVIDED
"AS IS"
,
WITHOUT
WARRANTY
OF
ANY
KIND
,
*
EXPRESS
OR
IMPLIED
,
INCLUDING
BUT
NOT
LIMITED
TO
THE
WARRANTIES
*
OF
MERCHANTABILITY
,
FITNESS
FOR
A
PARTICULAR
PURPOSE
AND
*
NONINFRINGEMENT
.
IN
NO
EVENT
SHALL
THE
AUTHORS
OR
COPYRIGHT
*
HOLDERS
BE
LIABLE
FOR
ANY
CLAIM
,
DAMAGES
OR
OTHER
LIABILITY
,
*
WHETHER
IN
AN
ACTION
OF
CONTRACT
,
TORT
OR
OTHERWISE
,
ARISING
*
FROM
,
OUT
OF
OR
IN
CONNECTION
WITH
THE
SOFTWARE
OR
THE
USE
OR
*
OTHER
DEALINGS
IN
THE
SOFTWARE
.
*/
/*
*
Device
Tree
file
for
Marvell
Armada
7040
Development
board
platform
*
Boot
device
:
NAND
,
0xE
(
SW3
)
*/
#
include
"armada-7040.dtsi"
/
{
model
=
"Marvell Armada 7040 DB board with NAND"
;
compatible
=
"marvell,armada7040-db-nand"
,
"marvell,armada7040-db"
,
"marvell,armada7040"
,
"marvell,armada-ap806-quad"
,
"marvell,armada-ap806"
;
chosen
{
stdout
-
path
=
"serial0:115200n8"
;
};
aliases
{
i2c0
=
&
cpm_i2c0
;
spi0
=
&
cpm_spi1
;
};
memory
@
00000000
{
device_type
=
"memory"
;
reg
=
<
0x0
0x0
0x0
0x80000000
>;
};
};
&
ap_pinctl
{
/*
MPP
Bus
:
*
SDIO
[
0
-
5
]
*
UART0
[
11
,
19
]
*/
/*
0
1
2
3
4
5
6
7
8
9
*/
pin
-
func
=
<
0x1
0x1
0x1
0x1
0x1
0x1
0x0
0x0
0x0
0x0
0x0
0x3
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x3
>;
};
&
uart0
{
status
=
"okay"
;
};
&
cpm_pcie2
{
status
=
"okay"
;
};
&
cpm_i2c0
{
pinctrl
-
names
=
"default"
;
pinctrl
-
0
=
<&
cpm_i2c0_pins
>;
status
=
"okay"
;
clock
-
frequency
=
<
100000
>;
};
&
cpm_pinctl
{
/*
MPP
Bus
:
*
AUDIO
[
0
-
5
]
*
GBE
[
6
-
11
]
*
SS_PWDN
[
12
]
*
NF_RBn
[
13
]
*
GPIO
[
14
]
*
DEV_BUS
[
15
-
27
]
*
SATA1
[
28
]
*
UART0
[
29
-
30
]
*
MSS_VTT_EN
[
31
]
*
SMI
[
32
,
34
]
*
XSMI
[
35
-
36
]
*
I2C
[
37
-
38
]
*
RGMII1
[
44
-
55
]
*
SD
[
56
-
61
]
*
GPIO
[
62
]
*/
/*
0
1
2
3
4
5
6
7
8
9
*/
pin
-
func
=
<
0x2
0x2
0x2
0x2
0x2
0x2
0x3
0x3
0x3
0x3
0x3
0x3
0x0
0x2
0x0
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x9
0xa
0xa
0x0
0x7
0x0
0x7
0x7
0x7
0x2
0x2
0x0
0x0
0x0
0x0
0x0
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0xe
0xe
0xe
0xe
0xe
0xe
0x0
>;
};
&
cpm_spi1
{
pinctrl
-
names
=
"default"
;
pinctrl
-
0
=
<&
cpm_spi0_pins
>;
status
=
"disabled"
;
spi
-
flash
@
0
{
#
address
-
cells
=
<
0x1
>;
#
size
-
cells
=
<
0x1
>;
compatible
=
"jedec,spi-nor"
;
reg
=
<
0x0
>;
spi
-
max
-
frequency
=
<
20000000
>;
partitions
{
compatible
=
"fixed-partitions"
;
#
address
-
cells
=
<
1
>;
#
size
-
cells
=
<
1
>;
partition
@
0
{
label
=
"U-Boot"
;
reg
=
<
0x0
0x200000
>;
};
partition
@
400000
{
label
=
"Filesystem"
;
reg
=
<
0x200000
0xe00000
>;
};
};
};
};
&
cpm_sata0
{
status
=
"okay"
;
};
&
cpm_usb3_0
{
status
=
"okay"
;
};
&
cpm_usb3_1
{
status
=
"okay"
;
};
&
cpm_comphy
{
phy0
{
phy
-
type
=
<
PHY_TYPE_SGMII2
>;
phy
-
speed
=
<
PHY_SPEED_3_125G
>;
};
phy1
{
phy
-
type
=
<
PHY_TYPE_USB3_HOST0
>;
phy
-
speed
=
<
PHY_SPEED_5G
>;
};
phy2
{
phy
-
type
=
<
PHY_TYPE_SGMII0
>;
phy
-
speed
=
<
PHY_SPEED_1_25G
>;
};
phy3
{
phy
-
type
=
<
PHY_TYPE_SATA1
>;
phy
-
speed
=
<
PHY_SPEED_5G
>;
};
phy4
{
phy
-
type
=
<
PHY_TYPE_USB3_HOST1
>;
phy
-
speed
=
<
PHY_SPEED_5G
>;
};
phy5
{
phy
-
type
=
<
PHY_TYPE_PEX2
>;
phy
-
speed
=
<
PHY_SPEED_5G
>;
};
};
&
cpm_nand
{
status
=
"okay"
;
};
&
cpm_utmi0
{
status
=
"okay"
;
};
&
cpm_utmi1
{
status
=
"okay"
;
};
&
ap_sdhci0
{
status
=
"okay"
;
bus
-
width
=
<
4
>;
no
-
1
-
8
-
v
;
non
-
removable
;
};
&
cpm_sdhci0
{
status
=
"okay"
;
bus
-
width
=
<
4
>;
no
-
1
-
8
-
v
;
non
-
removable
;
};
arch/arm/dts/armada-7040-db.dts
浏览文件 @
a2842129
...
...
@@ -42,6 +42,7 @@
/*
*
Device
Tree
file
for
Marvell
Armada
7040
Development
board
platform
*
Boot
device
:
SPI
NOR
,
0x32
(
SW3
)
*/
#
include
"armada-7040.dtsi"
...
...
@@ -158,7 +159,7 @@
&
cpm_comphy
{
phy0
{
phy
-
type
=
<
PHY_TYPE_SGMII
2
>;
phy
-
type
=
<
PHY_TYPE_SGMII
1
>;
phy
-
speed
=
<
PHY_SPEED_1_25G
>;
};
...
...
arch/arm/dts/armada-8040-db.dts
浏览文件 @
a2842129
...
...
@@ -83,28 +83,68 @@
&
cpm_pinctl
{
/*
MPP
Bus
:
*
[
0
-
31
]
=
0xff
:
Keep
default
CP0_shared_pins
:
*
[
11
]
CLKOUT_MPP_11
(
out
)
*
[
23
]
LINK_RD_IN_CP2CP
(
in
)
*
[
25
]
CLKOUT_MPP_25
(
out
)
*
[
29
]
AVS_FB_IN_CP2CP
(
in
)
*
[
32
,
34
]
SMI
*
[
31
]
GPIO
:
push
button
/
Wake
*
[
35
-
36
]
GPIO
*
[
37
-
38
]
I2C
*
[
40
-
41
]
SATA
[
0
/
1
]
_PRESENT_ACTIVEn
*
[
42
-
43
]
XSMI
*
[
44
-
55
]
RGMII1
*
[
56
-
62
]
SD
*
[
0
-
31
]
=
0xff
:
Keep
default
CP0_shared_pins
*
[
11
]
CLKOUT_MPP_11
(
out
)
*
[
23
]
LINK_RD_IN_CP2CP
(
in
)
*
[
25
]
CLKOUT_MPP_25
(
out
)
*
[
29
]
AVS_FB_IN_CP2CP
(
in
)
*
[
32
,
34
]
GE_MDIO
/
MDC
*
[
33
]
GPIO
:
GE_INT
#/
push
button
/
Wake
*
[
35
]
MSS_GPIO
[
3
]:
MSS_PWDN
*
[
36
]
MSS_GPIO
[
5
]:
MSS_VTT_EN
*
[
37
-
38
]
I2C0
*
[
39
]
PTP_CLK
*
[
40
-
41
]
SATA
[
0
/
1
]
_PRESENT_ACTIVEn
*
[
42
-
43
]
XG_MDC
/
XG_MDIO
(
XSMI
)
*
[
44
-
55
]
RGMII1
*
[
56
-
62
]
SD
*/
/*
0
1
2
3
4
5
6
7
8
9
*/
/*
0
1
2
3
4
5
6
7
8
9
*/
pin
-
func
=
<
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0
7
0
7
0
0
2
2
0
0
0
8
8
1
1
1
1
1
1
1
1
1
1
1
1
0xe
0xe
0xe
0xe
0xe
0xe
0xe
>;
0xff
0xff
0x7
0x0
0x7
0xa
0xa
0x2
0x2
0x5
0x9
0x9
0x8
0x8
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0xe
0xe
0xe
0xe
0xe
0xe
0xe
>;
};
&
cpm_comphy
{
/*
Serdes
Configuration
:
*
Lane
0
:
PCIe0
(
x1
)
*
Lane
1
:
SATA0
*
Lane
2
:
SFI
(
10
G
)
*
Lane
3
:
SATA1
*
Lane
4
:
USB3_HOST1
*
Lane
5
:
PCIe2
(
x1
)
*/
phy0
{
phy
-
type
=
<
PHY_TYPE_PEX0
>;
};
phy1
{
phy
-
type
=
<
PHY_TYPE_SATA0
>;
};
phy2
{
phy
-
type
=
<
PHY_TYPE_SFI
>;
};
phy3
{
phy
-
type
=
<
PHY_TYPE_SATA1
>;
};
phy4
{
phy
-
type
=
<
PHY_TYPE_USB3_HOST1
>;
};
phy5
{
phy
-
type
=
<
PHY_TYPE_PEX2
>;
};
};
/*
CON6
on
CP0
expansion
*/
&
cpm_pcie0
{
status
=
"okay"
;
};
&
cpm_pcie1
{
status
=
"disabled"
;
};
/*
CON5
on
CP0
expansion
*/
...
...
@@ -134,21 +174,69 @@
status
=
"okay"
;
};
&
cpm_utmi0
{
status
=
"okay"
;
};
&
cpm_utmi1
{
status
=
"okay"
;
};
&
cps_pinctl
{
/*
MPP
Bus
:
*
[
0
-
11
]
RGMII0
*
[
13
-
16
]
SPI1
*
[
27
,
31
]
GE_MDIO
/
MDC
*
[
32
-
62
]
=
0xff
:
Keep
default
CP1_shared_pins
:
*
[
0
-
11
]
RGMII0
*
[
13
-
16
]
SPI1
*
[
27
,
31
]
GE_MDIO
/
MDC
*
[
28
]
SATA1_PRESENT_ACTIVEn
*
[
29
-
30
]
UART0
*
[
32
-
62
]
=
0xff
:
Keep
default
CP1_shared_pins
*/
/*
0
1
2
3
4
5
6
7
8
9
*/
/*
0
1
2
3
4
5
6
7
8
9
*/
pin
-
func
=
<
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x
ff
0x3
0x3
0x3
0x3
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0x8
0x
ff
0xff
0x
ff
0x8
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0x3
0x3
0x
3
0x3
0x3
0x3
0x3
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0x8
0x
9
0xa
0x
A
0x8
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
>;
0xff
0xff
0xff
>;
};
&
cps_comphy
{
/*
Serdes
Configuration
:
*
Lane
0
:
PCIe0
(
x1
)
*
Lane
1
:
SATA0
*
Lane
2
:
SFI
(
10
G
)
*
Lane
3
:
SATA1
*
Lane
4
:
PCIe1
(
x1
)
*
Lane
5
:
PCIe2
(
x1
)
*/
phy0
{
phy
-
type
=
<
PHY_TYPE_PEX0
>;
};
phy1
{
phy
-
type
=
<
PHY_TYPE_SATA0
>;
};
phy2
{
phy
-
type
=
<
PHY_TYPE_SFI
>;
};
phy3
{
phy
-
type
=
<
PHY_TYPE_SATA1
>;
};
phy4
{
phy
-
type
=
<
PHY_TYPE_PEX1
>;
};
phy5
{
phy
-
type
=
<
PHY_TYPE_PEX2
>;
};
};
/*
CON6
on
CP1
expansion
*/
&
cps_pcie0
{
status
=
"okay"
;
};
&
cps_pcie1
{
status
=
"okay"
;
};
/*
CON5
on
CP1
expansion
*/
...
...
@@ -200,86 +288,6 @@
status
=
"okay"
;
};
&
cpm_comphy
{
/*
*
Serdes
Configuration
:
*
Lane
0
:
SGMII2
*
Lane
1
:
USB3_HOST0
*
Lane
2
:
KR
(
10
G
)
*
Lane
3
:
SATA1
*
Lane
4
:
USB3_HOST1
*
Lane
5
:
PEX2x1
*/
phy0
{
phy
-
type
=
<
PHY_TYPE_SGMII2
>;
phy
-
speed
=
<
PHY_SPEED_3_125G
>;
};
phy1
{
phy
-
type
=
<
PHY_TYPE_USB3_HOST0
>;
};
phy2
{
phy
-
type
=
<
PHY_TYPE_KR
>;
};
phy3
{
phy
-
type
=
<
PHY_TYPE_SATA1
>;
};
phy4
{
phy
-
type
=
<
PHY_TYPE_USB3_HOST1
>;
};
phy5
{
phy
-
type
=
<
PHY_TYPE_PEX2
>;
};
};
&
cps_comphy
{
/*
*
Serdes
Configuration
:
*
Lane
0
:
SGMII2
*
Lane
1
:
USB3_HOST0
*
Lane
2
:
KR
(
10
G
)
*
Lane
3
:
SATA1
*
Lane
4
:
Unconnected
*
Lane
5
:
PEX2x1
*/
phy0
{
phy
-
type
=
<
PHY_TYPE_SGMII2
>;
phy
-
speed
=
<
PHY_SPEED_3_125G
>;
};
phy1
{
phy
-
type
=
<
PHY_TYPE_USB3_HOST0
>;
};
phy2
{
phy
-
type
=
<
PHY_TYPE_KR
>;
};
phy3
{
phy
-
type
=
<
PHY_TYPE_SATA1
>;
};
phy4
{
phy
-
type
=
<
PHY_TYPE_UNCONNECTED
>;
};
phy5
{
phy
-
type
=
<
PHY_TYPE_PEX2
>;
};
};
&
cpm_utmi0
{
status
=
"okay"
;
};
&
cpm_utmi1
{
status
=
"okay"
;
};
&
cps_utmi0
{
status
=
"okay"
;
};
...
...
arch/arm/dts/armada-8040-mcbin.dts
浏览文件 @
a2842129
...
...
@@ -99,7 +99,7 @@
*
[
54
]
2.5
G
SFP
LOS
*
[
55
]
Micro
SD
card
detect
*
[
56
-
61
]
Micro
SD
*
[
62
]
CP1
KR
SFP
FAULT
*
[
62
]
CP1
SFI
SFP
FAULT
*/
/*
0
1
2
3
4
5
6
7
8
9
*/
pin
-
func
=
<
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
...
...
@@ -163,7 +163,7 @@
*
Lane
1
:
PCIe0
(
x4
)
*
Lane
2
:
PCIe0
(
x4
)
*
Lane
3
:
PCIe0
(
x4
)
*
Lane
4
:
KR
(
10
G
)
*
Lane
4
:
SFI
(
10
G
)
*
Lane
5
:
SATA1
*/
phy0
{
...
...
@@ -179,7 +179,7 @@
phy
-
type
=
<
PHY_TYPE_PEX0
>;
};
phy4
{
phy
-
type
=
<
PHY_TYPE_
KR
>;
phy
-
type
=
<
PHY_TYPE_
SFI
>;
};
phy5
{
phy
-
type
=
<
PHY_TYPE_SATA1
>;
...
...
@@ -264,15 +264,15 @@
&
cps_comphy
{
/*
*
CP1
Serdes
Configuration
:
*
Lane
0
:
SGMII
2
*
Lane
0
:
SGMII
1
*
Lane
1
:
SATA
0
*
Lane
2
:
USB
HOST
0
*
Lane
3
:
SATA1
*
Lane
4
:
KR
(
10
G
)
*
Lane
4
:
SFI
(
10
G
)
*
Lane
5
:
SGMII3
*/
phy0
{
phy
-
type
=
<
PHY_TYPE_SGMII
2
>;
phy
-
type
=
<
PHY_TYPE_SGMII
1
>;
phy
-
speed
=
<
PHY_SPEED_1_25G
>;
};
phy1
{
...
...
@@ -285,7 +285,7 @@
phy
-
type
=
<
PHY_TYPE_SATA1
>;
};
phy4
{
phy
-
type
=
<
PHY_TYPE_
KR
>;
phy
-
type
=
<
PHY_TYPE_
SFI
>;
};
phy5
{
phy
-
type
=
<
PHY_TYPE_SGMII3
>;
...
...
arch/arm/dts/armada-cp110-master.dtsi
浏览文件 @
a2842129
...
...
@@ -253,7 +253,7 @@
reg = <0x580000 0x1000>, /* utmi-unit */
<0x440420 0x4>, /* usb-cfg */
<0x440440 0x4>; /* utmi-cfg */
utmi-port = <UTMI_PHY_TO_USB_HOST0>;
utmi-port = <UTMI_PHY_TO_USB
3
_HOST0>;
status = "disabled";
};
...
...
@@ -262,7 +262,7 @@
reg = <0x581000 0x1000>, /* utmi-unit */
<0x440420 0x4>, /* usb-cfg */
<0x440444 0x4>; /* utmi-cfg */
utmi-port = <UTMI_PHY_TO_USB_HOST1>;
utmi-port = <UTMI_PHY_TO_USB
3
_HOST1>;
status = "disabled";
};
...
...
@@ -273,6 +273,20 @@
dma-coherent;
status = "disabled";
};
cpm_nand: nand@720000 {
compatible = "marvell,mvebu-pxa3xx-nand";
reg = <0x720000 0x100>;
#address-cells = <1>;
clocks = <&cpm_syscon0 1 2>;
nand-enable-arbiter;
num-cs = <1>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
status = "disabled";
};
};
cpm_pcie0: pcie@f2600000 {
...
...
arch/arm/dts/armada-cp110-slave.dtsi
浏览文件 @
a2842129
...
...
@@ -254,7 +254,7 @@
reg = <0x580000 0x1000>, /* utmi-unit */
<0x440420 0x4>, /* usb-cfg */
<0x440440 0x4>; /* utmi-cfg */
utmi-port = <UTMI_PHY_TO_USB_HOST0>;
utmi-port = <UTMI_PHY_TO_USB
3
_HOST0>;
status = "disabled";
};
};
...
...
arch/arm/mach-mvebu/arm64-common.c
浏览文件 @
a2842129
...
...
@@ -8,6 +8,7 @@
#include <dm.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <pci.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/arch/cpu.h>
...
...
@@ -147,5 +148,10 @@ int arch_early_init_r(void)
/* Cause the SATA device to do its early init */
uclass_first_device
(
UCLASS_AHCI
,
&
dev
);
#ifdef CONFIG_DM_PCI
/* Trigger PCIe devices detection */
pci_init
();
#endif
return
0
;
}
arch/arm/mach-mvebu/armada8k/cpu.c
浏览文件 @
a2842129
...
...
@@ -110,3 +110,21 @@ void reset_cpu(ulong ignored)
reg
&=
~
(
1
<<
RFU_SW_RESET_OFFSET
);
writel
(
reg
,
RFU_GLOBAL_SW_RST
);
}
/*
* TODO - implement this functionality using platform
* clock driver once it gets available
* Return NAND clock in Hz
*/
u32
mvebu_get_nand_clock
(
void
)
{
unsigned
long
NAND_FLASH_CLK_CTRL
=
0xF2440700UL
;
unsigned
long
NF_CLOCK_SEL_MASK
=
0x1
;
u32
reg
;
reg
=
readl
(
NAND_FLASH_CLK_CTRL
);
if
(
reg
&
NF_CLOCK_SEL_MASK
)
return
400
*
1000000
;
else
return
250
*
1000000
;
}
arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c
浏览文件 @
a2842129
...
...
@@ -13,8 +13,6 @@
#include "high_speed_env_spec.h"
#include "sys_env_lib.h"
#define SERDES_VERION "2.0"
u8
selectors_serdes_rev1_map
[
LAST_SERDES_TYPE
][
MAX_SERDES_LANES
]
=
{
/* 0 1 2 3 4 5 */
{
0x1
,
0x1
,
NA
,
NA
,
NA
,
NA
},
/* PEX0 */
...
...
arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
浏览文件 @
a2842129
...
...
@@ -27,7 +27,7 @@
*/
struct
cfg_seq
serdes_seq_db
[
SERDES_LAST_SEQ
];
#define SERDES_VERION "2.0"
#define SERDES_VER
S
ION "2.0"
#define ENDED_OK "High speed PHY - Ended Successfully\n"
#define LINK_WAIT_CNTR 100
...
...
@@ -1416,7 +1416,7 @@ int serdes_phy_config(void)
DEBUG_INIT_FULL_S
(
"
\n
### ctrl_high_speed_serdes_phy_config ###
\n
"
);
DEBUG_INIT_S
(
"High speed PHY - Version: "
);
DEBUG_INIT_S
(
SERDES_VERION
);
DEBUG_INIT_S
(
SERDES_VER
S
ION
);
DEBUG_INIT_S
(
"
\n
"
);
/* Init serdes sequences DB */
...
...
arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
浏览文件 @
a2842129
...
...
@@ -14,7 +14,7 @@
#include "high_speed_env_spec.h"
#include "board_env_spec.h"
#define SERDES_VERION "2.1.5"
#define SERDES_VER
S
ION "2.1.5"
#define ENDED_OK "High speed PHY - Ended Successfully\n"
static
const
u8
serdes_cfg
[][
SERDES_LAST_UNIT
]
=
BIN_SERDES_CFG
;
...
...
@@ -285,12 +285,12 @@ int serdes_phy_config(void)
if
(
reg_read
(
REG_BOOTROM_ROUTINE_ADDR
)
&
(
1
<<
REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS
))
{
DEBUG_INIT_S
(
"High speed PHY - Version: "
);
DEBUG_INIT_S
(
SERDES_VERION
);
DEBUG_INIT_S
(
SERDES_VER
S
ION
);
DEBUG_INIT_S
(
" - 2nd boot - Skip
\n
"
);
return
MV_OK
;
}
DEBUG_INIT_S
(
"High speed PHY - Version: "
);
DEBUG_INIT_S
(
SERDES_VERION
);
DEBUG_INIT_S
(
SERDES_VER
S
ION
);
DEBUG_INIT_S
(
" (COM-PHY-V20)
\n
"
);
/*
...
...
arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c
浏览文件 @
a2842129
...
...
@@ -5,7 +5,6 @@
*/
#include <common.h>
#include <i2c.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
...
...
cmd/mvebu/bubt.c
浏览文件 @
a2842129
...
...
@@ -309,16 +309,17 @@ static int is_spi_active(void)
#ifdef CONFIG_CMD_NAND
static
int
nand_burn_image
(
size_t
image_size
)
{
int
ret
,
block_size
;
nand_info_t
*
nand
;
int
ret
;
uint32_t
block_size
;
struct
mtd_info
*
nand
;
int
dev
=
nand_curr_device
;
if
((
dev
<
0
)
||
(
dev
>=
CONFIG_SYS_MAX_NAND_DEVICE
)
||
(
!
nand_info
[
dev
]
.
name
))
{
(
!
nand_info
[
dev
]
->
name
))
{
puts
(
"
\n
no devices available
\n
"
);
return
-
ENOMEDIUM
;
}
nand
=
&
nand_info
[
dev
];
nand
=
nand_info
[
dev
];
block_size
=
nand
->
erasesize
;
/* Align U-Boot size to currently used blocksize */
...
...
@@ -334,8 +335,8 @@ static int nand_burn_image(size_t image_size)
printf
(
"Done!
\n
"
);
/* Write the image to flash */
printf
(
"Writing
image:..."
);
printf
(
"&image_size = 0x%p
\n
"
,
(
void
*
)
&
image_size
);
printf
(
"Writing
%d bytes from 0x%lx to offset 0 ... "
,
(
int
)
image_size
,
get_load_addr
()
);
ret
=
nand_write
(
nand
,
0
,
&
image_size
,
(
void
*
)
get_load_addr
());
if
(
ret
)
printf
(
"Error!
\n
"
);
...
...
configs/db-88f6820-amc_defconfig
浏览文件 @
a2842129
...
...
@@ -36,6 +36,8 @@ CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
# CONFIG_MMC is not set
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
...
...
configs/mvebu_db-88f7040-nand_defconfig
0 → 100644
浏览文件 @
a2842129
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MVEBU_ARMADA_8K=y
CONFIG_DEFAULT_DEVICE_TREE="armada-7040-db-nand"
CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_LATE_INIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_NAND=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_MVEBU_BUBT=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_BLOCK_CACHE=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MVEBU_NAND_BOOT=y
CONFIG_NAND_PXA3XX=y
CONFIG_PHYLIB=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCIE_DW_MVEBU=y
CONFIG_MVEBU_COMPHY_SUPPORT=y
CONFIG_PINCTRL=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xf0512000
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_SMBIOS_MANUFACTURER=""
drivers/mtd/nand/pxa3xx_nand.c
浏览文件 @
a2842129
...
...
@@ -9,6 +9,7 @@
#include <common.h>
#include <malloc.h>
#include <fdtdec.h>
#include <nand.h>
#include <linux/errno.h>
#include <asm/io.h>
...
...
@@ -19,6 +20,8 @@
#include "pxa3xx_nand.h"
DECLARE_GLOBAL_DATA_PTR
;
#define TIMEOUT_DRAIN_FIFO 5
/* in ms */
#define CHIP_DELAY_TIMEOUT 200
#define NAND_STOP_DELAY 40
...
...
@@ -1510,8 +1513,6 @@ static int alloc_nand_resource(struct pxa3xx_nand_info *info)
chip
->
cmdfunc
=
nand_cmdfunc
;
}
info
->
mmio_base
=
(
void
__iomem
*
)
MVEBU_NAND_BASE
;
/* Allocate a buffer to allow flash detection */
info
->
buf_size
=
INIT_BUFFER_SIZE
;
info
->
data_buff
=
kmalloc
(
info
->
buf_size
,
GFP_KERNEL
);
...
...
@@ -1533,17 +1534,62 @@ fail_disable_clk:
static
int
pxa3xx_nand_probe_dt
(
struct
pxa3xx_nand_info
*
info
)
{
struct
pxa3xx_nand_platform_data
*
pdata
;
const
void
*
blob
=
gd
->
fdt_blob
;
int
node
=
-
1
;
pdata
=
kzalloc
(
sizeof
(
*
pdata
),
GFP_KERNEL
);
if
(
!
pdata
)
return
-
ENOMEM
;
pdata
->
enable_arbiter
=
1
;
pdata
->
num_cs
=
1
;
/* Get address decoding nodes from the FDT blob */
do
{
node
=
fdt_node_offset_by_compatible
(
blob
,
node
,
"marvell,mvebu-pxa3xx-nand"
);
if
(
node
<
0
)
break
;
/* Bypass disabeld nodes */
if
(
!
fdtdec_get_is_enabled
(
blob
,
node
))
continue
;
info
->
pdata
=
pdata
;
/* Get the first enabled NAND controler base address */
info
->
mmio_base
=
(
void
__iomem
*
)
fdtdec_get_addr_size_auto_noparent
(
blob
,
node
,
"reg"
,
0
,
NULL
,
true
);
return
0
;
pdata
->
num_cs
=
fdtdec_get_int
(
blob
,
node
,
"num-cs"
,
1
);
if
(
pdata
->
num_cs
!=
1
)
{
error
(
"pxa3xx driver supports single CS only
\n
"
);
break
;
}
if
(
fdtdec_get_bool
(
blob
,
node
,
"nand-enable-arbiter"
))
pdata
->
enable_arbiter
=
1
;
if
(
fdtdec_get_bool
(
blob
,
node
,
"nand-keep-config"
))
pdata
->
keep_config
=
1
;
/*
* ECC parameters.
* If these are not set, they will be selected according
* to the detected flash type.
*/
/* ECC strength */
pdata
->
ecc_strength
=
fdtdec_get_int
(
blob
,
node
,
"nand-ecc-strength"
,
0
);
/* ECC step size */
pdata
->
ecc_step_size
=
fdtdec_get_int
(
blob
,
node
,
"nand-ecc-step-size"
,
0
);
info
->
pdata
=
pdata
;
/* Currently support only a single NAND controller */
return
0
;
}
while
(
node
>=
0
);
return
-
EINVAL
;
}
static
int
pxa3xx_nand_probe
(
struct
pxa3xx_nand_info
*
info
)
...
...
@@ -1603,8 +1649,8 @@ void board_nand_init(void)
int
ret
;
info
=
kzalloc
(
sizeof
(
*
info
)
+
sizeof
(
*
host
)
*
CONFIG_SYS_MAX_NAND_DEVICE
,
GFP_KERNEL
);
sizeof
(
*
host
)
*
CONFIG_SYS_MAX_NAND_DEVICE
,
GFP_KERNEL
);
if
(
!
info
)
return
;
...
...
drivers/net/mvpp2.c
浏览文件 @
a2842129
...
...
@@ -2618,6 +2618,13 @@ static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
static
void
mvpp2_bm_bufs_free
(
struct
udevice
*
dev
,
struct
mvpp2
*
priv
,
struct
mvpp2_bm_pool
*
bm_pool
)
{
int
i
;
for
(
i
=
0
;
i
<
bm_pool
->
buf_num
;
i
++
)
{
/* Allocate buffer back from the buffer manager */
mvpp2_read
(
priv
,
MVPP2_BM_PHY_ALLOC_REG
(
bm_pool
->
id
));
}
bm_pool
->
buf_num
=
0
;
}
...
...
@@ -5501,6 +5508,21 @@ static int mvpp2_probe(struct udevice *dev)
return
0
;
}
/*
* Empty BM pool and stop its activity before the OS is started
*/
static
int
mvpp2_remove
(
struct
udevice
*
dev
)
{
struct
mvpp2_port
*
port
=
dev_get_priv
(
dev
);
struct
mvpp2
*
priv
=
port
->
priv
;
int
i
;
for
(
i
=
0
;
i
<
MVPP2_BM_POOLS_NUM
;
i
++
)
mvpp2_bm_pool_destroy
(
dev
,
priv
,
&
priv
->
bm_pools
[
i
]);
return
0
;
}
static
const
struct
eth_ops
mvpp2_ops
=
{
.
start
=
mvpp2_start
,
.
send
=
mvpp2_send
,
...
...
@@ -5512,9 +5534,11 @@ static struct driver mvpp2_driver = {
.
name
=
"mvpp2"
,
.
id
=
UCLASS_ETH
,
.
probe
=
mvpp2_probe
,
.
remove
=
mvpp2_remove
,
.
ops
=
&
mvpp2_ops
,
.
priv_auto_alloc_size
=
sizeof
(
struct
mvpp2_port
),
.
platdata_auto_alloc_size
=
sizeof
(
struct
eth_pdata
),
.
flags
=
DM_FLAG_ACTIVE_DMA
,
};
/*
...
...
drivers/pci/pcie_dw_mvebu.c
浏览文件 @
a2842129
...
...
@@ -487,13 +487,13 @@ static int pcie_dw_mvebu_probe(struct udevice *dev)
/* Don't register host if link is down */
if
(
!
pcie_dw_mvebu_pcie_link_up
(
pcie
->
ctrl_base
,
LINK_SPEED_GEN_3
))
{
printf
(
"PCIE-%d: Link down
\n
"
,
dev
->
seq
);
return
-
ENODEV
;
}
else
{
printf
(
"PCIE-%d: Link up (Gen%d-x%d, Bus%d)
\n
"
,
dev
->
seq
,
pcie_dw_get_link_speed
(
pcie
->
ctrl_base
),
pcie_dw_get_link_width
(
pcie
->
ctrl_base
),
hose
->
first_busno
);
}
printf
(
"PCIE-%d: Link up (Gen%d-x%d, Bus%d)
\n
"
,
dev
->
seq
,
pcie_dw_get_link_speed
(
pcie
->
ctrl_base
),
pcie_dw_get_link_width
(
pcie
->
ctrl_base
),
hose
->
first_busno
);
pcie_dw_regions_setup
(
pcie
);
/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
...
...
drivers/phy/marvell/comphy.h
浏览文件 @
a2842129
...
...
@@ -86,6 +86,7 @@ struct comphy_map {
u32
speed
;
u32
invert
;
bool
clk_src
;
bool
end_point
;
};
struct
chip_serdes_phy_config
{
...
...
@@ -96,7 +97,7 @@ struct chip_serdes_phy_config {
void
__iomem
*
hpipe3_base_addr
;
u32
comphy_lanes_count
;
u32
comphy_mux_bitcount
;
u32
c
omphy
_index
;
u32
c
p
_index
;
};
/* Register helper functions */
...
...
drivers/phy/marvell/comphy_core.c
浏览文件 @
a2842129
...
...
@@ -37,7 +37,7 @@ static char *get_type_string(u32 type)
"SGMII1"
,
"SGMII2"
,
"SGMII3"
,
"QSGMII"
,
"USB3_HOST0"
,
"USB3_HOST1"
,
"USB3_DEVICE"
,
"XAUI0"
,
"XAUI1"
,
"XAUI2"
,
"XAUI3"
,
"RXAUI0"
,
"RXAUI1"
,
"
KR
"
};
"RXAUI0"
,
"RXAUI1"
,
"
SFI"
,
"IGNORE
"
};
if
(
type
<
0
||
type
>
PHY_TYPE_MAX
)
return
"invalid"
;
...
...
@@ -90,9 +90,6 @@ void comphy_print(struct chip_serdes_phy_config *chip_cfg,
for
(
lane
=
0
;
lane
<
chip_cfg
->
comphy_lanes_count
;
lane
++
,
comphy_map_data
++
)
{
if
(
comphy_map_data
->
type
==
PHY_TYPE_UNCONNECTED
)
continue
;
if
(
comphy_map_data
->
speed
==
PHY_SPEED_INVALID
)
{
printf
(
"Comphy-%d: %-13s
\n
"
,
lane
,
get_type_string
(
comphy_map_data
->
type
));
...
...
@@ -113,6 +110,7 @@ static int comphy_probe(struct udevice *dev)
int
subnode
;
int
lane
;
int
last_idx
=
0
;
static
int
current_idx
;
/* Save base addresses for later use */
chip_cfg
->
comphy_base_addr
=
(
void
*
)
dev_get_addr_index
(
dev
,
0
);
...
...
@@ -166,6 +164,8 @@ static int comphy_probe(struct udevice *dev)
blob
,
subnode
,
"phy-invert"
,
PHY_POLARITY_NO_INVERT
);
comphy_map_data
[
lane
].
clk_src
=
fdtdec_get_bool
(
blob
,
subnode
,
"clk-src"
);
comphy_map_data
[
lane
].
end_point
=
fdtdec_get_bool
(
blob
,
subnode
,
"end_point"
);
if
(
comphy_map_data
[
lane
].
type
==
PHY_TYPE_INVALID
)
{
printf
(
"no phy type for lane %d, setting lane as unconnected
\n
"
,
lane
+
1
);
...
...
@@ -174,13 +174,13 @@ static int comphy_probe(struct udevice *dev)
lane
++
;
}
/* Save
comphy
index for MultiCP devices (A8K) */
chip_cfg
->
c
omphy_index
=
dev
->
seq
;
/* Save
CP
index for MultiCP devices (A8K) */
chip_cfg
->
c
p_index
=
current_idx
++
;
/* PHY power UP sequence */
chip_cfg
->
ptr_comphy_chip_init
(
chip_cfg
,
comphy_map_data
);
/* PHY print SerDes status */
if
(
of_machine_is_compatible
(
"marvell,armada8040"
))
printf
(
"Comphy chip #%d:
\n
"
,
chip_cfg
->
c
omphy
_index
);
printf
(
"Comphy chip #%d:
\n
"
,
chip_cfg
->
c
p
_index
);
comphy_print
(
chip_cfg
,
comphy_map_data
);
/*
...
...
@@ -189,7 +189,7 @@ static int comphy_probe(struct udevice *dev)
if
(
of_machine_is_compatible
(
"marvell,armada8040"
))
last_idx
=
1
;
if
(
chip_cfg
->
c
omphy
_index
==
last_idx
)
{
if
(
chip_cfg
->
c
p
_index
==
last_idx
)
{
/* Initialize dedicated PHYs (not muxed SerDes lanes) */
comphy_dedicated_phys_init
();
}
...
...
drivers/phy/marvell/comphy_cp110.c
浏览文件 @
a2842129
此差异已折叠。
点击以展开。
drivers/phy/marvell/comphy_hpipe.h
浏览文件 @
a2842129
...
...
@@ -49,6 +49,9 @@
#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4
#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \
(0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7
#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \
(0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)
#define SD_EXTERNAL_STATUS0_REG 0x18
#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
...
...
@@ -105,9 +108,15 @@
#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1
#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \
(0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6
#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \
(0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET)
#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7
#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \
(0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11
#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \
(0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET)
#define HPIPE_G1_SET_1_REG 0x038
#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
...
...
@@ -116,22 +125,96 @@
#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3
#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \
(0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
#define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6
#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \
(0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
#define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8
#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \
(0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET)
#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10
#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \
(0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
#define HPIPE_G2_SETTINGS_1_REG 0x040
#define HPIPE_G3_SETTINGS_1_REG 0x048
#define HPIPE_G3_RX_SELMUPI_OFFSET 0
#define HPIPE_G3_RX_SELMUPI_MASK \
(0x7 << HPIPE_G3_RX_SELMUPI_OFFSET)
#define HPIPE_G3_RX_SELMUPF_OFFSET 3
#define HPIPE_G3_RX_SELMUPF_MASK \
(0x7 << HPIPE_G3_RX_SELMUPF_OFFSET)
#define HPIPE_G3_SETTING_BIT_OFFSET 13
#define HPIPE_G3_SETTING_BIT_MASK \
(0x1 << HPIPE_G3_SETTING_BIT_OFFSET)
#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11
#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \
(0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET)
#define HPIPE_G2_SET_0_REG 0x3c
#define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1
#define HPIPE_G2_SET_0_G2_TX_AMP_MASK \
(0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET)
#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6
#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \
(0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET)
#define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7
#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \
(0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET)
#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11
#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \
(0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET)
#define HPIPE_G2_SET_1_REG 0x040
#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0
#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \
(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3
#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \
(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET)
#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6
#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \
(0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)
#define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8
#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \
(0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET)
#define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10
#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \
(0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET)
#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11
#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \
(0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET)
#define HPIPE_G3_SET_0_REG 0x44
#define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1
#define HPIPE_G3_SET_0_G3_TX_AMP_MASK \
(0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET)
#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6
#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \
(0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET)
#define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7
#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \
(0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET)
#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11
#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \
(0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET)
#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12
#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \
(0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET)
#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15
#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \
(0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET)
#define HPIPE_G3_SET_1_REG 0x048
#define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0
#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \
(0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET)
#define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3
#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \
(0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET)
#define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6
#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \
(0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET)
#define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8
#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \
(0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET)
#define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10
#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \
(0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET)
#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11
#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \
(0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET)
#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13
#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \
(0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET)
#define HPIPE_LOOPBACK_REG 0x08c
#define HPIPE_LOOPBACK_SEL_OFFSET 1
...
...
@@ -144,6 +227,9 @@
#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
#define HPIPE_INTERFACE_GEN_MAX_MASK \
(0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
#define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12
#define HPIPE_INTERFACE_DET_BYPASS_MASK \
(0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET)
#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
#define HPIPE_INTERFACE_LINK_TRAIN_MASK \
(0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
...
...
@@ -166,6 +252,16 @@
#define HPIPE_VTHIMPCAL_CTRL_REG 0x104
#define HPIPE_VDD_CAL_CTRL_REG 0x114
#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5
#define HPIPE_EXT_SELLV_RXSAMPL_MASK \
(0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
#define HPIPE_VDD_CAL_0_REG 0x108
#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15
#define HPIPE_CAL_VDD_CONT_MODE_MASK \
(0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET)
#define HPIPE_PCIE_REG0 0x120
#define HPIPE_PCIE_IDLE_SYNC_OFFSET 12
#define HPIPE_PCIE_IDLE_SYNC_MASK \
...
...
@@ -212,9 +308,29 @@
#define HPIPE_PWR_CTR_SFT_RST_MASK \
(0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
#define HPIPE_SPD_DIV_FORCE_REG 0x154
#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7
#define HPIPE_TXDIGCK_DIV_FORCE_MASK \
(0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET)
#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8
#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \
(0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET)
#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10
#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \
(0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET)
#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13
#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \
(0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET)
#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15
#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \
(0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET)
#define HPIPE_PLLINTP_REG1 0x150
#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6
#define HPIPE_RX_SAMPLER_OS_GAIN_MASK \
(0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET)
#define HPIPE_SMAPLER_OFFSET 12
#define HPIPE_SMAPLER_MASK \
(0x1 << HPIPE_SMAPLER_OFFSET)
...
...
@@ -227,12 +343,54 @@
#define HPIPE_TX_REG1_SLC_EN_MASK \
(0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
#define HPIPE_PWR_CTR_DTL_REG 0x184
#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
#define HPIPE_PWR_CTR_DTL_REG 0x184
#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0
#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \
(0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET)
#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1
#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \
(0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET)
#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
(0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
#define HPIPE_RX_REG3 0x188
#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4
#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \
(0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET)
#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10
#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \
(0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET)
#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12
#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \
(0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET)
#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14
#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \
(1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET)
#define HPIPE_PHASE_CONTROL_REG 0x188
#define HPIPE_OS_PH_OFFSET_OFFSET 0
#define HPIPE_OS_PH_OFFSET_MASK \
(0x7f << HPIPE_OS_PH_OFFSET_OFFSET)
#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7
#define HPIPE_OS_PH_OFFSET_FORCE_MASK \
(0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
#define HPIPE_OS_PH_VALID_OFFSET 8
#define HPIPE_OS_PH_VALID_MASK \
(0x1 << HPIPE_OS_PH_VALID_OFFSET)
#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214
#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7
#define HPIPE_TRAIN_PAT_NUM_MASK \
(0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET)
#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220
#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12
#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \
(0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET)
#define HPIPE_DME_REG 0x228
#define HPIPE_DME_ETHERNET_MODE_OFFSET 7
#define HPIPE_DME_ETHERNET_MODE_MASK \
(0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)
#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
...
...
@@ -259,6 +417,9 @@
#define HPIPE_PCIE_REG3 0x290
#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4
#define HPIPE_RX_TRAIN_TIMER_OFFSET 0
#define HPIPE_RX_TRAIN_TIMER_MASK \
(0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET)
#define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11
#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \
(0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
...
...
@@ -279,6 +440,23 @@
#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7
#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \
(0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8
#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \
(0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET)
#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9
#define HPIPE_TX_TRAIN_PAT_SEL_MASK \
(0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)
#define HPIPE_CDR_CONTROL_REG 0x418
#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
(0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6
#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \
(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
...
...
@@ -291,10 +469,25 @@
#define HPIPE_TX_SWEEP_PRESET_EN_MASK \
(0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
#define HPIPE_G1_SETTINGS_3_REG 0x440
#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
#define HPIPE_G1_SETTINGS_3_REG 0x440
#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0
#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \
(0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET)
#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4
#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \
(0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET)
#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7
#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \
(0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET)
#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
(0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12
#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \
(0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET)
#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14
#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \
(0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET)
#define HPIPE_G1_SETTINGS_4_REG 0x444
#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8
...
...
@@ -302,9 +495,22 @@
(0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
#define HPIPE_G2_SETTINGS_3_REG 0x448
#define HPIPE_G2_SETTINGS_4_REG 0x44C
#define HPIPE_G2_SETTINGS_4_REG 0x44c
#define HPIPE_G2_DFE_RES_OFFSET 8
#define HPIPE_G2_DFE_RES_MASK \
(0x3 << HPIPE_G2_DFE_RES_OFFSET)
#define HPIPE_G3_SETTING_3_REG 0x450
#define HPIPE_G3_FFE_CAP_SEL_OFFSET 0
#define HPIPE_G3_FFE_CAP_SEL_MASK \
(0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET)
#define HPIPE_G3_FFE_RES_SEL_OFFSET 4
#define HPIPE_G3_FFE_RES_SEL_MASK \
(0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET)
#define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7
#define HPIPE_G3_FFE_SETTING_FORCE_MASK \
(0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET)
#define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12
#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \
(0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
...
...
@@ -317,6 +523,16 @@
#define HPIPE_G3_DFE_RES_MASK \
(0x3 << HPIPE_G3_DFE_RES_OFFSET)
#define HPIPE_TX_PRESET_INDEX_REG 0x468
#define HPIPE_TX_PRESET_INDEX_OFFSET 0
#define HPIPE_TX_PRESET_INDEX_MASK \
(0xf << HPIPE_TX_PRESET_INDEX_OFFSET)
#define HPIPE_DFE_CONTROL_REG 0x470
#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14
#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \
(0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET)
#define HPIPE_DFE_CTRL_28_REG 0x49C
#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
...
...
@@ -327,6 +543,11 @@
#define HPIPE_G1_SETTING_5_G1_ICP_MASK \
(0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
#define HPIPE_G3_SETTING_5_REG 0x548
#define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0
#define HPIPE_G3_SETTING_5_G3_ICP_MASK \
(0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET)
#define HPIPE_LANE_CONFIG0_REG 0x600
#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \
...
...
@@ -349,6 +570,9 @@
#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \
(0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3
#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \
(0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET)
#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
#define HPIPE_LANE_CFG4_DFE_OVER_MASK \
(0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
...
...
@@ -366,6 +590,17 @@
#define HPIPE_CFG_UPDATE_POLARITY_MASK \
(0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
#define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8
#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0
#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \
(0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1
#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \
(0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2
#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \
(0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
#define HPIPE_RST_CLK_CTRL_REG 0x704
#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \
...
...
drivers/phy/marvell/comphy_mux.c
浏览文件 @
a2842129
...
...
@@ -27,6 +27,10 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data,
for
(
lane
=
0
;
lane
<
comphy_max_lanes
;
lane
++
,
comphy_map_data
++
,
mux_data
++
)
{
/* Don't check ignored COMPHYs */
if
(
comphy_map_data
->
type
==
PHY_TYPE_IGNORE
)
continue
;
mux_opt
=
mux_data
->
mux_values
;
for
(
opt
=
0
,
valid
=
0
;
opt
<
mux_data
->
max_lane_values
;
opt
++
,
mux_opt
++
)
{
...
...
@@ -83,6 +87,9 @@ static void comphy_mux_reg_write(struct comphy_mux_data *mux_data,
for
(
lane
=
0
;
lane
<
comphy_max_lanes
;
lane
++
,
comphy_map_data
++
,
mux_data
++
)
{
if
(
comphy_map_data
->
type
==
PHY_TYPE_IGNORE
)
continue
;
offset
=
lane
*
bitcount
;
mask
=
(((
1
<<
bitcount
)
-
1
)
<<
offset
);
value
=
(
comphy_mux_get_mux_value
(
mux_data
,
...
...
include/configs/db-88f6820-amc.h
浏览文件 @
a2842129
...
...
@@ -27,13 +27,6 @@
#define CONFIG_CMD_ENV
#define CONFIG_CMD_PCI
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
#define CONFIG_SYS_I2C_SLAVE 0x0
#define CONFIG_SYS_I2C_SPEED 100000
/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_BUS 1
#define CONFIG_SF_DEFAULT_SPEED 1000000
...
...
include/configs/mvebu_armada-8k.h
浏览文件 @
a2842129
...
...
@@ -76,11 +76,22 @@
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
/* Environment in SPI NOR flash */
#ifdef CONFIG_MVEBU_SPI_BOOT
#define CONFIG_ENV_IS_IN_SPI_FLASH
/* Environment in NAND flash */
#elif defined(CONFIG_MVEBU_NAND_BOOT)
#define CONFIG_ENV_IS_IN_NAND
#endif
#define CONFIG_ENV_OFFSET 0x180000
/* as Marvell U-Boot version */
#define CONFIG_ENV_SIZE (64 << 10)
/* 64KiB */
#define CONFIG_ENV_SECT_SIZE (64 << 10)
/* 64KiB sectors */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_USE_FLASH_BBT
/*
* Ethernet Driver configuration
*/
...
...
include/dt-bindings/comphy/comphy_data.h
浏览文件 @
a2842129
...
...
@@ -13,10 +13,11 @@
#define PHY_SPEED_3G 3
#define PHY_SPEED_3_125G 4
#define PHY_SPEED_5G 5
#define PHY_SPEED_6G 6
#define PHY_SPEED_6_25G 7
#define PHY_SPEED_10_3125G 8
#define PHY_SPEED_MAX 9
#define PHY_SPEED_5_15625G 6
#define PHY_SPEED_6G 7
#define PHY_SPEED_6_25G 8
#define PHY_SPEED_10_3125G 9
#define PHY_SPEED_MAX 10
#define PHY_SPEED_INVALID 0xff
#define PHY_TYPE_UNCONNECTED 0
...
...
@@ -42,8 +43,9 @@
#define PHY_TYPE_XAUI3 20
#define PHY_TYPE_RXAUI0 21
#define PHY_TYPE_RXAUI1 22
#define PHY_TYPE_KR 23
#define PHY_TYPE_MAX 24
#define PHY_TYPE_SFI 23
#define PHY_TYPE_IGNORE 24
#define PHY_TYPE_MAX 25
#define PHY_TYPE_INVALID 0xff
#define PHY_POLARITY_NO_INVERT 0
...
...
@@ -52,9 +54,9 @@
#define PHY_POLARITY_ALL_INVERT \
(PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT)
#define UTMI_PHY_TO_USB_HOST0 0
#define UTMI_PHY_TO_USB_HOST1 1
#define UTMI_PHY_TO_USB
_DEVICE0
2
#define UTMI_PHY_TO_USB
3
_HOST0 0
#define UTMI_PHY_TO_USB
3
_HOST1 1
#define UTMI_PHY_TO_USB
3_DEVICE0
2
#define UTMI_PHY_INVALID 0xff
#endif
/* _COMPHY_DATA_H_ */
...
...
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