- 29 8月, 2009 15 次提交
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由 Kumar Gala 提交于
There are really no differences between all the 85xx linker scripts so we can just move to a single common one. Board code is still able to override the common one if need be. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Poonam Aggrwal 提交于
P1020 is another member of QorIQ series of processors which falls in ULE category. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities. Also the SOC is pin compatible with P2020 Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Poonam Aggrwal 提交于
The code base adds P1 & P2 RDB platforms support. The folder and file names can cater to future SOCs of P1/P2 family. P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series. Tested following on P2020RDB: 1. eTSECs 2. DDR, NAND, NOR, I2C. Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Poonam Aggrwal 提交于
The number of CPUs are getting detected dynamically by checking the processor SVR value. Also removed CONFIG_NUM_CPUS references from all the platforms with 85xx/86xx processors. This can help to use the same u-boot image across the platforms. Also revamped and corrected few Freescale Copyright messages. Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Poonam Aggrwal 提交于
Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c and moved to cpu/mpc8xxx/cpu.c(new file) Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Alex Dubov 提交于
Move files belonging to the STx boards into common vendor directory and update the Makefile to reflect this. Signed-off-by: NAlex Dubov <oakad@yahoo.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Peter Tyser 提交于
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
For historic reasons we had defined some additional PLATFORM_CPPFLAGS like: PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 However these are all captured in the config.h and thus redudant. Also moved common 86xx flags into cpu/mpc86xx/config.mk. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
For historic reasons we had defined some additional PLATFORM_CPPFLAGS like: PLATFORM_CPPFLAGS += -DCONFIG_E500=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 However these are all captured in the config.h and thus redudant. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary to allow for larger memory sizes. Signed-off-by: NKumar Gala <galak@kernel.crashing.org> Acked-by: NWolfgang Denk <wd@denx.de> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Every platform that calls fsl_pci_init calls pci_setup_indirect before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 28 8月, 2009 1 次提交
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- 27 8月, 2009 10 次提交
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由 Sandeep Paulraj 提交于
This patch adds 4 BIT ECC support in the DaVinci NAND driver. Tested on both the DM355 and DM365. Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com> Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Sandeep Paulraj 提交于
This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to support 4-bit ECC on TI DaVinci devices with large page (up to 2K) NAND chips. This ECC mode is similar to NAND_ECC_HW, with the exception of read_page API that first reads the OOB area, reads the data in chunks, feeds the ECC from OOB area to the ECC hw engine and perform any correction on the data as per the ECC status reported by the engine. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-new-ecc-mode-ecc_hw_oob_first.patchSigned-off-by: NSandeep Paulraj <s-paulraj@ti.com> Signed-off-by: NSneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Ilya Yanok 提交于
Driver for NFC NAND controller found on Freescale's MX2 and MX3 processors. Ported from Linux. Tested only with i.MX27 but should works with other MX2 and MX3 processors too. Signed-off-by: NIlya Yanok <yanok@emcraft.com> Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Sandeep Paulraj 提交于
This patch adds a new "page" parameter to all NAND read_page/read_page_raw APIs. The read_page API for the new mode ECC_HW_OOB_FIRST requires the page information to send the READOOB command and read the OOB area before the data area. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-page-parameter-to-all-read_page-read_page_raw-apis.patch WE would like this to become part of the u-boot GIT as well Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com> Signed-off-by: NSneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Heiko Schocher 提交于
Signed-off-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Kyungmin Park 提交于
Remove unused read_spareram and add unlock_all as kernel does Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Matthias Kaehlcke 提交于
Add KB9202 NAND driver Signed-off-by: NMatthias Kaehlcke <matthias@kaehlcke.net> Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Kyungmin Park 提交于
Remove unused read_spareram and add unlock_all as kernel does Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
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由 Eric Millbrandt 提交于
Signed-off-by: NEric Millbrandt <emillbrandt@dekaresearch.com>
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- 26 8月, 2009 14 次提交
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由 TsiChung Liew 提交于
Change %08lX to %08X in board.c. Remove unused variable 'oscillator' in mcf5227x/cpu_init.c and 'scm2' in mcf532x/cpu_init.c. Provide argument type cast in drivers/dma/MCD_dmaApi.c. Signed-off-by: NTsiChung Liew <tsicliew@gmail.com>
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由 TsiChung Liew 提交于
The compile error was caused by a recent patch. Affected platforms - M5253DEMO.h, M5253EVBE.h, and M54455EVB.h. Adding the _IO_BASE automatically defined to 0 in asm-m68k/io.h if it isn't set in platform configuration file. Signed-off-by: NTsiChung Liew <tsicliew@gmail.com>
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由 Niklaus Giger 提交于
see http://www.jedec.org/download/search/jep106Z.pdf Add some second source legacy flash chips 256x8. Signed-off-by: NNiklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Wolfgang Denk 提交于
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由 Kim Phillips 提交于
if you don't have firmware installed for the PHY to come to life, this wait can be painful - let's give the option to avoid it if we want. Signed-off-by: NKim Phillips <kim.phillips@freescale.com> Acked-by: NAndy Fleming <afleming@freescale.com> Signed-off-by: NBen Warren <biggerbadderben@gmail.com>
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由 Robin Getz 提交于
Optionally add RFC 2349 "Transfer Size Option", so we can minimize the time spent sending data over the UART (now print a single line during a tftp transfer). - If turned on (CONFIG_TFTP_TSIZE), U-Boot asks for the size of the file. - if receives the file size, a single line (50 chars) are printed. one hash mark == 2% of the file downloaded. - if it doesn't receive the file size (the server doesn't support RFC 2349, prints standard hash marks (one mark for each UDP frame). Signed-off-by: NRobin Getz <rgetz@blackfin.uclinux.org> Signed-off-by: NBen Warren <biggerbadderben@gmail.com>
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由 Robin Getz 提交于
Add a simple print for the Blackfin's Ethernet Rx function, so we can debug incomming Ethernet functions easier. Signed-off-by: NRobin Getz <rgetz@blackfin.uclinux.org> Signed-off-by: NBen Warren <biggerbadderben@gmail.com>
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由 Ben Warren 提交于
All in-tree boards that use this controller have CONFIG_NET_MULTI added Also: - changed CONFIG_DRIVER_CS8900 to CONFIG_CS8900 - changed CS8900_BASE to CONFIG_CS8900_BASE - changed CS8900_BUS?? to CONFIG_CS8900_BUS?? - cleaned up line lengths - modified VCMA9 command function that accesses the device - removed MAC address initialization from lib_arm/board.c Signed-off-by: NBen Warren <biggerbadderben@gmail.com> Tested-by: NWolfgang Denk <wd@denx.de> Acked-by: NWolfgang Denk <wd@denx.de>
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由 Alessandro Rubini 提交于
This chooses 4kB data size for both TFTP and NFS, as an example about how to use support for IP fragments. Signed-off-by: NAlessandro Rubini <rubini@gnudd.com> Signed-off-by: NBen Warren <biggerbadderben@gmail.com>
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由 Alessandro Rubini 提交于
To take advantage of defragmented packets, the config file can define CONFIG_NFS_READ_SIZE to override the 1kB default. No support is there for an environment variable by now. Signed-off-by: NAlessandro Rubini <rubini@gnudd.com> Signed-off-by: NBen Warren <biggerbadderben@gmail.com>
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由 Alessandro Rubini 提交于
Increasing the block size is useful if CONFIG_IP_DEFRAG is used. Howerver, the last fragments in a burst may overflow the receiving ethernet, so the default is left at 1468, with thre new CONFIG_TFTP_BLOCKSIZE for config files. Further, "tftpblocksize" can be set in the environment. Signed-off-by: NAlessandro Rubini <rubini@gnudd.com> Signed-off-by: NBen Warren <biggerbadderben@gmail.com>
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