Signed-off-by: NDavid Feng <fenghua@phytium.com.cn>

Signed-off-by: NDavid Feng <fenghua@phytium.com.cn>

Signed-off-by: NDavid Feng <fenghua@phytium.com.cn>

Byte offset of Ethernet mac address read from e-fuse are wrong so DHCP is
not working on some boards, modifying the offset to read properly.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>

Following commit "arm: omap3: Enable clocks for peripherals only if they are
used" (f33b9bd3) it is now necessary to enable
clocks for GPIO banks explicitly. On cm_t35, GPIO bank 5 is necessary for
scf0403 lcd support.

Enable GPIO bank 5 clocks.
Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Acked-by: NIgor Grinberg <grinberg@compulab.co.il>

Commit f33b9bd3 breaks boards
which do not explicitly enable the gpio clocks. This causes
the twister spl to hang, since it uses the no longer enabled
gpio 55. Add CONFIG_OMAP3_GPIO_2 to unbrick the board.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: NStefano Babic <sbabic@denx.de>

commit f9095aac793aa8917ab9b915c5d449e6dc8d3d30, "mtd: nand:
omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-scheme"
removed CONFIG_SPL_NAND_SOFTECC from the tam3517 common config,
causing the spl nand boot to fail. Add it back, so derived
boards boot again.

Cc: Pekon Gupta <pekon@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Raphael Assenat <raph@8d.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: NStefano Babic <sbabic@denx.de>

The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ
and Tom Rix's email has long been bouncing.
Signed-off-by: NTom Rini <trini@ti.com>

With the changes to make OOBFREE/ECCPOS configurable but default to
larger, we need to set these config options for the space savings they
provide.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: NTom Rini <trini@ti.com>

Due to the i2c mux rework in u-boot we now have only to specify the
busnumber and not the whole mux configuration.
Signed-off-by: NHolger Brunck <holger.brunck@keymile.com>
Acked-by: NHeiko Schocher <hs@denx.de>

The board is similar to the standard km_kirkwood board. From a
u-boot point of view, the only difference is an increased
256 MiB DRAM (128M16). A board based on this design is for
example the SUP12.
Signed-off-by: NKarlheinz Jerg <karlheinz.jerg@keymile.com>
Signed-off-by: NHolger Brunck <holger.brunck@keymile.com>

Signed-off-by: NLuka Perkov <luka@openwrt.org>
CC: Prafulla Wadaskar <prafulla@marvell.com>
Acked-By: NPrafulla Wadaskar <prafulla@marvell.com>

Conflicts:
	include/micrel.h

The conflict above was trivial, caused by four lines being
added in both branches with different whitepace.

Enable fuse supply before fuse programming and disable after.
Signed-off-by: NSergey Alyoshin <alyoshin.s@gmail.com>
Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

The enable_fec_anatop_clock method should be available for all MX6
variant as it is not MX6 SoloLite specific. This moves the code out of
the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC
instead.
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
Acked-by: NStefano Babic <sbabic@denx.de>

This patch fixes allow for the DeviceTree and initrd relocation fixing
the boot of FSL 3.10.9-1.0.0-alpha kernel.

This changes following boards:

 - mx6sabreauto
 - mx6sabresd
 - wandboard
 - udoo
 - nitrogen6x
 - cgtqmx6eval

The reasoning, as explained by Hui Liu, is:

,----
| The FDT blob will be placed at DDR physical addr: 0x11000000. When Linux kernel
| Boot up, it will decompress the compressed kernel image and place the decompressed
| kernel image at the low end of the DDR memory and start running from it. If the
| decompressed kernel image is bigger for example than 16M, it may over written the
| fdt blob which u-boot loaded to the DDR memory @0x11000000 with fdt_addr=0x11000000
|
| To expand the fdt_addr from 0x11000000 to 0x18000000, which can avoid the override
| Since we will not likely have one kernel image larger than 128MB.
`----
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
Acked-by: NStefano Babic <sbabic@denx.de>

This adds following new targets:

 - update_nand_kernel
 - update_nand_fdt
 - update_nand_filesystem

and to avoid confusion, the 'update_nand_full' has been renamed to
'update_nand_firmware_full'.
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>

This reads the kernel, ftd and boot into ubifs filesystem. While on
that, the SD firmware filename definition has been moved next to the
other SD related commands.
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com>

Using 512k for fdt partition allow it to be aligned with the other
small partitions and 512k erase block size.
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
Acked-by: NStefano Babic <sbabic@denx.de>

The macro allows easy setting in per-pin, as for example:

,----
| imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION);
`----

The IOMUX_CONFIG_SION allows for reading PAD value from PSR register.

The following quote from the datasheet:

,----
| ...
| 28.4.2.2 GPIO Write Mode
| The programming sequence for driving output signals should be as follows:
| 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need
| to read loopback pad value through PSR
| 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b).
| 3. Write value to data register (GPIO_DR).
| ...
`----

This fixes the gpio_get_value to properly work when a GPIO is set for
output and has no conflicts.

Thanks for Benoît Thébaudeau <benoit.thebaudeau@advansee.com>, Fabio
Estevam <fabio.estevam@freescale.com> and Eric Bénard
<eric@eukrea.com> for helping to properly trace this down.
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
Acked-by: NStefano Babic <sbabic@denx.de>

As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator
in order to save power.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NJason Liu <r64343@freescale.com>
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

When changing LDO voltages we need to wait for the required amount of time
for the voltage to settle.

Also, as the timer is still not available when arch_cpu_init() is called, we
need to call it later at board_postclk_init() phase.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Introduce set_ldo_voltage() so that all three LDO regulators can be configured.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V.
Add a 25 mV margin and set it to 1.175V.

This also matches the VDDSOC voltages for 792MHz operation that the kernel configures:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Since ROM may modify the LDO ramp up time according to fuse setting,
it is safer to reset the ramp up field to its default value of 00:

00: 64 cycles of 24MHz clock;
01: 128 cycles of 24MHz clock;
02: 256 cycles of 24MHz clock;
03: 512 cycles of 24MHz clock;
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NJason Liu <r64343@freescale.com>
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

set_vddsoc() is not used anywhere else, so make it static.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Add CONFIG_CMD_FUSE option, so that the fuse API can be used.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

When using the fuse API in U-boot user must calculate the 'bank' and 'word'
values.

Provide a real example on how to calculate such values for the mx6q.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

This patch add uuid disk to defualt partions necessary to
restore gpt partitions and fixes mmcdev environmental variable.
Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This fix is necessary after increased by one the number
of adapters in s3c24x0 driver.

Tested on Trats and Trats2.
Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

When variable size SPL is used, the BL1 expects the SPL to be
encapsulated differently: instead of putting the checksum at a fixed
offset in the SPL blob, prepend the blob with a header including the
size and the checksum.

The enhancements include
	- adding a command line option, '--vs' to indicate the need for the
	variable size encapsulation
	- padding the fixed size encapsulated blob with 0xff instead of random
	memory contents
	- do not silently truncate the input file, report error instead
	- no need to explicitly closing files/freeing memory, this all happens
	on exit; removing cleanups it makes code clearer
	- profuse commenting
	- modify Makefile to allow enabling the new feature per board
Signed-off-by: NVadim Bendebury <vbendeb@chromium.org>
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Adding initial config for SMDK5420 to build and boot U-Boot
over Exynos based SMDK5420.
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch adds dts support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Adding the base patch for Exynos based SMDK5420.
This shall enable compilation and basic boot support for
SMDK5420.
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Adds code in pinmux and gpio framework to support Exynos5420.
Signed-off-by: NNaveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch intends to add DDR3 initialization code for Exynos5420.
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Add dmc and phy_control register structure for 5420.
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>