- 10 10月, 2014 13 次提交
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由 Masahiro Yamada 提交于
These boards have been orphaned for more than 6 months. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
This board has been orphaned for more than 6 months. It is the last board defining CONFIG_APM821XX. The code inside #ifdef CONFIG_APM821XX should be removed too. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
This board has been orphaned for more than 6 months. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
These boards have been orphaned for more than 6 months. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
In some cases, the last lines of SPL or TPL are not output to a file. The entries remaining in the "unmatched" variable must be flushed. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Khoronzhuk, Ivan 提交于
The definitions for div ratio supposed to be in hex and were added in dec by mistake. Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
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由 Roger Quadros 提交于
At least on OMAP, init_sata() no longer performs scsi_scan() so we must do it explicitly here. Cc: Dan Murphy <dmurphy@ti.com> Signed-off-by: NRoger Quadros <rogerq@ti.com>
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由 Roger Quadros 提交于
scsi_scan() must be called as part of scsi_init() and not as part of sata_init(). Signed-off-by: NRoger Quadros <rogerq@ti.com>
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由 Roger Quadros 提交于
On OMAP platforms, SATA controller provides the SCSI subsystem so implement scsi_init(). Get rid of the unnecessary sata_init() call from dra7xx-evm and omap5-uevm board files. Signed-off-by: NRoger Quadros <rogerq@ti.com>
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由 Roger Quadros 提交于
The DMA/FIS buffers are set in ahci_port_start() which is called after ahci_host_init(). So don't start the DMA engine here (i.e. don't set FIS_RX) This fixes the following error at kernel boot on OMAP platforms (e.g. DRA7x) WARNING: CPU: 0 PID: 0 at drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x260/0x358() 44000000.ocp:L3 Custom Error: MASTER SATA TARGET GPMC (Idle): Data Access in User mode during Functional access Signed-off-by: NRoger Quadros <rogerq@ti.com>
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由 Stefan Herbrechtsmeier 提交于
Commit 12cc5437 'omap3: overo: Select fdtfile for expansion board' wrongly missed the operator in the fdtfile test. Update the test to only overwrite an empty fdtfile environment variable. Signed-off-by: NStefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
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由 York Sun 提交于
Commit 294b91a5 moved initr_malloc earlier than initr_unlock_ram_in_cache. This causes issue on T4240. It may be related to locked L1 d-cache and unlocked L2 cache. D- cache could and should be unlock earlier for normal operation. This patch moves initr_unlock_ram_in_cache before initr_malloc. It has been verified on the following boards, in which only T4240QDS suffered and has been since fixed: T4240QDS, T2080QDS, P5040DS, P4080DS, MPC8572DS, MPC8536DS, MPC8641HPCN, B4860QDS. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: Scott Wood <scottwood@freescale.com> CC: Simon Glass <sjg@chromium.org> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Ian Campbell 提交于
On a couple of platforms I've tripped over long PXE append lines overflowing this array, due to having CONFIG_SYS_CBSIZE == 256. When doing preseeded Debian installs it's pretty trivial to exceed that. Since the symptom can be a silent hang or a crash add a check. Of course the affected boards would also need an increased CBSIZE to actually work. Note that due to the printing of the final bootargs string CONFIG_SYS_PBSIZE also needs to be sufficiently large. Signed-off-by: NIan Campbell <ian.campbell@citrix.com> [trini: Use %zd not %d in printf for all args] Signed-off-by: NTom Rini <trini@ti.com>
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- 08 10月, 2014 1 次提交
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由 Hans de Goede 提交于
In order for the gmac nic to work reliable on the Bananapi, we need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" of the GMAC clk register (0x01c20164) to 3. Without this about 9 out of 10 ethernet packets get lost, with this setting there is no packet loss. So far setting these bits is only necessary on the Bananapi, so this commit solves this with a bit of #ifdef CONFIG_BANANAPI code. If in the future we need to do something similar for other boards, we can create a specific CONFIG_FOO option for this then. Reported-by: NKarsten Merker <merker@debian.org> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Tested-by: NKarsten Merker <merker@debian.org> Tested-by: NZoltan HERPAI <wigyori@openwrt.org> Tested-by: NTony Zhang <tony.zhang@lemaker.org> Acked-by: NIan Campbell <ijc@hellion.org.uk>
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- 07 10月, 2014 8 次提交
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由 Anthony Felice 提交于
Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: NAnthony Felice <tony.felice@timesys.com> [rebased on v2014.10-rc2] Signed-off-by: NStefan Agner <stefan@agner.ch>
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由 Albert ARIBAUD 提交于
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@ti.com>
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git://git.denx.de/u-boot-socfpga由 Tom Rini 提交于
Fix a trivial conflict in dw_mmc.c after talking with Marek. Conflicts: drivers/mmc/dw_mmc.c Signed-off-by: NTom Rini <trini@ti.com>
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由 Eric Nelson 提交于
Without NULL termination, various commands will read past the end of input. In particular, this was noticed with error() calls in cb_getvar and simple_strtoul() in cb_download. Since the download callback happens elsewhere, the 4k buffer should always be sufficient to handle command arguments. Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
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由 Daniel Mack 提交于
This bit allows the MUSB controller to negotiate for high-speed mode when the device is reset by the hub. If unset, Babble errors occur with high-speed mass storage devices right after the first packet. This condition is not caught by the interrupt handles in U-Boot, so no recovery is done, and the USB communication is stuck. To fix this, set the bit unconditionally, not only for CONFIG_USB_GADGET_DUALSPEED but also for host-only modes. Signed-off-by: NDaniel Mack <zonque@gmail.com>
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- 06 10月, 2014 18 次提交
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由 Marek Vasut 提交于
Enable and use the CONFIG_CMD_FS_GENERIC to avoid hard-coding the filesystem type into the environment. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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由 Pavel Machek 提交于
Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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由 Marek Vasut 提交于
Reorganize and cleanup the configuration file for SoCFPGA. There is no functional change after this cleanup. This was necessary, since the file was a wild mess and it was impossible to make sense of it's content, let alone change something without breaking some other thing. This patch puts the contents on par with regular U-Boot standards. Also remove unused preprocessor symbols CONFIG_SINGLE_BOOTOADER and CONFIG_USE_IRQ, which is undefined by default. Finally, do logical reordering of the defines in the file so it's much more readable. The reordering was also necessary for the splitting as the initial one was messy. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
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由 Marek Vasut 提交于
Add command to enable and disable the bridges between HPS and FPGA. This patch does have a checkpatch issue with the assembler portion, checkpatch correctly complains that there should be no whitespace before quoted newline. I do not agree that fixing this specific checkpatch issue will improve the readability, thus this one is not addressed. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de>
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由 Marek Vasut 提交于
Move icache_enable() and dcache_enable() function calls from board code into the CPU code and into the enable_caches() function. This is how the cache enabling code was designed to work. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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由 Chin Liang See 提交于
Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit. Enable the bootz command as zImage is used instead uImage. Signed-off-by: NChin Liang See <clsee@altera.com> Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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由 Chin Liang See 提交于
Enable the DesignWare MMC controller driver support for SOCFPGA Cyclone5 dev kit Signed-off-by: NChin Liang See <clsee@altera.com> Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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由 Pavel Machek 提交于
Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA . The code sets the access permissions for the CPU to the AMBA slaves such that the CPU can access them in both secure and non-secure mode. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
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由 Marek Vasut 提交于
Configure the PL310 address filter to make sure DRAM is mapped to 0x0. This code also configures the "remap" register of NIC-301 and sets the required 'mpuzero' bit. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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由 Marek Vasut 提交于
Add register definition for the NIC-301 used on SoCFPGA. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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由 Marek Vasut 提交于
Add the Snoop Control Unit register definition file. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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由 Marek Vasut 提交于
Enable the PL310 L2 cache controller support for the SoCFPGA. With the cache related issues resolved, this is safe to be done. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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由 Marek Vasut 提交于
The code is now fixed to the point where we can safely enable the L1 data cache. Enable the D-Cache and set it as write-alloc. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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由 Marek Vasut 提交于
The Cortex-A9 has 32-byte long L1 cachelines. Define this value. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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由 Marek Vasut 提交于
Add missing system manager bits from Altera U-Boot to make the code comparable. These are the bits which depend on the FPGA manager. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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由 Marek Vasut 提交于
Add function to enable and disable FPGA bridges. This code is used by the FPGA manager to disable the bridges before programming the FPGA and will later be also used by the initialization code for the chip to put the chip into well defined state during startup. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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由 Pavel Machek 提交于
Add code necessary to program the FPGA part of SoCFPGA from U-Boot with an RBF blob. This patch also integrates the code into the FPGA driver framework in U-Boot so it can be used via the 'fpga' command. Signed-off-by: NPavel Machek <pavel@denx.de> Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move the not-CPU specific stuff into drivers/fpga/ and base this on the cleaned up altera FPGA support.
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由 Marek Vasut 提交于
Cosmetic change to the checkboard() function output. Align the output with the rest of initial output produced by U-Boot. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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