Communication with some SPI slaves just won't cut it if these delays
(before the beginning, and after the end of a transfer) are not added to
the Chip Select signal.

These are a straight copy from Linux:
Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
drivers/spi/spi-fsl-dspi.c
Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
[Rebased]
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

This reverts commit 5d3a21df, reversing
changes made to 56d37f1c.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649Signed-off-by: NTom Rini <trini@konsulko.com>

At present the SiFive FU540 RAM driver uses hard-coded memory base
address and size to initialize the DDR controller. This may not be
true when this driver is used on another board based on FU540.

Update the driver to read the memory information from DT and use
that during the initialization.
Signed-off-by: NBin Meng <bin.meng@windriver.com>
Reviewed-by: NLeo Liang <ycliang@andestech.com>
Reviewed-by: NPragnesh Patel <pragnesh.patel@sifive.com>

The commit 4cc24aea ("serial: Add missing Kconfig dependencies for
debug consoles") has added incorrect dependency for SIFIVE debug uart which
should depend on SIFIVE driver instead of PL01x.

Fixes: 4cc24aea ("serial: Add missing Kconfig dependencies for debug consoles")
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bin.meng@windriver.com>
Reviewed-by: NLeo Liang <ycliang@andestech.com>
Reviewed-by: NSean Anderson <seanga2@gmail.com>

Per the DT binding, <mask> and <value> property can have either one
or both, and if <value> is missing, <mask> should be used, which is
what current U-Boot sysreset_syscon driver supports.

This adds support to the <value> property to the driver, and <mask>
semantics is updated to really be a mask to the value if both exist.
Signed-off-by: NBin Meng <bin.meng@windriver.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NPragnesh Patel <pragnesh.patel@sifive.com>

Per the DT binding, <offset> is a required property. Let's abort
the probe if it is missing. For the <mask> property, current codes
assume a default value of zero, which is not correct either.
Signed-off-by: NBin Meng <bin.meng@windriver.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NPragnesh Patel <pragnesh.patel@sifive.com>

Drop the legacy PHY driver and it's associated code since
the PHY handling driver now part of Generic PHY framework.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Now, we have a PCIe PHY driver as part of the Generic
PHY framework. Let's use it instead of legacy PHY driver.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Add the Rockchip PCIe PHY driver as part of
Generic PHY framework.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

The empty function define should not be in the header file, or else the
build will error with function multi definition after CONFIG_RAM_ROCKCHIP_DEBUG
is disabled.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

Right now all these debug statements are printing on the
console to make sure proper dram initialization happens.  

Mark them into RAM_ROCKCHIP_DEBUG would be more meaningful
and work like before since the RAM_ROCKCHIP_DEBUG is by
default yet.

No functionality changes.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

stride debug is already present in sdram_common.c via
RAM_ROCKCHIP_DEBUG.

So, drop the redundant debug stride code in rk3399 driver.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Add support for the RK3328 SPI controller
Signed-off-by: NJohannes Krottmayer <krjdev@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Add SPI support for the RK3328 clock driver
Signed-off-by: NJohannes Krottmayer <krjdev@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  expression dev;
  @@
  -devfdt_get_addr(dev)
  +dev_read_addr(dev)
  </smpl>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This cast is unneeded.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Use the _ptr suffixed variant instead of casting. Also, convert it to
dev_read_addr_ptr(), which is safe to CONFIG_OF_LIVE.

One curious part is an error check like follows in
drivers/watchdog/omap_wdt.c:

    priv->regs = (struct wd_timer *)devfdt_get_addr(dev);
    if (!priv->regs)
            return -EINVAL;

devfdt_get_addr() returns FDT_ADDR_T_NONE (i.e. -1) on error.
So, this code does not catch any error in DT parsing.

dev_read_addr_ptr() returns NULL on error, so this error check
will work.

I generated this commit by the following command:

 $ find . -name .git -prune -o -name '*.[ch]' -type f -print | \
   xargs sed -i -e 's/([^*)]*\*)devfdt_get_addr(/dev_read_addr_ptr(/'

I manually fixed drivers/usb/host/ehci-mx6.c
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Introduce an soc_ti_k3_driver that allows identification and selection
of SoC specific data based on the JTAG ID register for device
identification, as described for AM65x[0] and J721E[1] devices.

[0] http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf
[1] http://www.ti.com/lit/ug/spruil1a/spruil1a.pdfSigned-off-by: NDave Gerlach <d-gerlach@ti.com>

Add a sandbox SOC driver, and some tests for the SOC uclass.
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

Introduce UCLASS_SOC to be used for SOC identification and attribute
matching based on the SoC ID info. This allows drivers to be provided
for SoCs to retrieve SoC identifying information and also for matching
device attributes for selecting SoC specific data.

This is useful for other device drivers that may need different
parameters or quirks enabled depending on the specific device variant in
use.
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

These functions should not modify the device. Convert them to const so
that callers don't need to cast if they have a const udevice *.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Fix an over-length line in this function.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add device table for new Micron SPI NAND devices, which have multiple
dies.

Also, enable support to select the dies.
Signed-off-by: NShivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: NJagan Teki <jagan@amarulasolutions.com>

Add device table for M70A series Micron SPI NAND devices.
Signed-off-by: NShivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: NJagan Teki <jagan@amarulasolutions.com>

Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with
the Continuous Read mode.

Some of the Micron SPI NAND devices have the "Continuous Read" feature
enabled by default, which does not fit the subsystem needs.

In this mode, the READ CACHE command doesn't require the starting column
address. The device always output the data starting from the first
column of the cache register, and once the end of the cache register
reached, the data output continues through the next page. With the
continuous read mode, it is possible to read out the entire block using
a single READ command, and once the end of the block reached, the output
pins become High-Z state. However, during this mode the read command
doesn't output the OOB area.

Hence, we disable the feature at probe time.
Signed-off-by: NShivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: NJagan Teki <jagan@amarulasolutions.com>

Add device table for M79A and M78A series Micron SPI NAND devices.
Signed-off-by: NShivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: NJagan Teki <jagan@amarulasolutions.com>

Add the SPI NAND device MT29F2G01ABAGD series number, size and voltage
details as a comment.
Signed-off-by: NShivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: NJagan Teki <jagan@amarulasolutions.com>

In order to add new Micron SPI NAND devices, we generalized the OOB
layout structure and function names.
Signed-off-by: NShivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: NJagan Teki <jagan@amarulasolutions.com>

Some boards don't care about the ordering of ACPI code fragments. Change
the warning to a debug message.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
family.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

The types of "offset" and "size" of "struct mtd_partition" are uint64_t,
while mtd_parse_partitions() uses int to work with these values. When
the offset reaches 2GB, it is interpreted as a negative value, which
leads to error messages like

mtd: partition "<partition name>" is out of reach -- disabled

eg. when using the "ubi part" command.

Fix this by using uint64_t for cur_off and cur_sz.
Signed-off-by: NMartin Kaistra <martin.kaistra@linutronix.de>
Reviewed-by: NKurt Kanzenbach <kurt@linutronix.de>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Some code was not converted by coccinelle, somehow.

I manually fixed up the remaining, and comments, README docs.
Signed-off-by: NMasahiro Yamada <masahiroy@kernel.org>
[trini: Add arch/arm/mach-davinci/include/mach/sdmmc_defs.h and
        include/fdt_support.h]
Signed-off-by: NTom Rini <trini@konsulko.com>

The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:

  It's a **mistake** to use typedef for structures and pointers.

Besides, using typedef for structures is annoying when you try to make
headers self-contained.

Let's say you have the following function declaration in a header:

  void foo(bd_t *bd);

This is not self-contained since bd_t is not defined.

To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h>

  #include <asm/u-boot.h>
  void foo(bd_t *bd);

Then, the include direcective pulls in more bloat needlessly.

If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:

  struct bd_info;
  void foo(struct bd_info *bd);

Right, typedef'ing bd_t is a mistake.

I used coccinelle to generate this commit.

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  typedef bd_t;
  @@
  -bd_t
  +struct bd_info
  </smpl>
Signed-off-by: NMasahiro Yamada <masahiroy@kernel.org>

This converts the following to Kconfig:
   CONFIG_MXC_UART
Signed-off-by: NTom Rini <trini@konsulko.com>
Acked-by: NPeng Fan <peng.fan@nxp.com>

This should ideally be used by all x86 boards in U-Boot. Enable it by
default. If some boards don't use it, the cost is small.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

The FSP-S changes the ITSS priorities. The code that tries to save it
before running FSP-S and restore it afterwards does not work as U-Boot
relocates in between the save and restore. This means that the driver
data saved before relocation is lost and the new driver just sees zeroes.

Fix this by allocating space in the relocated memory for the ITSS data.
Save it there and access it from the driver after relocation.

This fixes interrupt handling on coral.

Also drop the log_msg_ret() in irq_first_device_type() since this function
can be called speculatively in places where we are not sure if there is
an interrupt controller of that type. The resulting log errors are
confusing when there is no error.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>

These registers need to be accesses from ACPI code, so move them to the
header file.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

The P2SB bus needs to be hidden in some cases so that it does not get
auto-configured by Linux. Add a method for this.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>

Update the PCI driver to generate ACPI information so that Linux has the
full information about each I2C bus.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NHeiko Schocher <hs@denx.de>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
[bmeng: Correct one typo in dw_i2c_gen_speed_config() comments]
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>

Add a few of these calls to make it easier to see where an error occurs,
if CONFIG_LOG_ERROR_RETURN is enabled.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>