- 13 2月, 2014 4 次提交
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由 Masahiro Yamada 提交于
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com> Cc: David Feng <fenghua@phytium.com.cn> Acked-by: NScott Wood <scottwood@freescale.com>
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由 Stephen Warren 提交于
The entries in config.mk were needed so that U-Boot could be built with an old version of the Raspberry Pi Foundation's toolchain. Without them, the build would error out with: ...-ld: error: .../libgcc.a(_bswapsi2.o) uses VFP register arguments, u-boot does not However, none of the 3 toolchains in the latest version of their tools.git, nor the Ubuntu/Linaro ARM compilers in at least Ubuntu Quantal or Saucy, need these options set in order to compile a working U-Boot. Hence, remove the options for simplicity. Reported-by: NTom Rini <trini@ti.com> Signed-off-by: NStephen Warren <swarren@wwwdotorg.org> Reviewed-by: NAndreas Färber <afaerber@suse.de>
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由 Stephen Warren 提交于
U-Boot names the Raspberry Pi board rpi_b. This means that the common expression for DTB filename ${soc}-${board}.dtb expands to bcm2835-rpi_b.dtb. However, the DTB generated by the Linux kernel is bcm2835-rpi-b.dtb. Set $fdtfile in U-Boot's environment so that scripts look for the correct DTB filename. An alternative would be to rename the U-Boot board to rpi-b. However, that change would be far more invasive, and end up affecting users (i.e they'd have to change their U-Boot build commands). Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
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由 Albert ARIBAUD 提交于
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- 10 2月, 2014 2 次提交
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由 Inha Song 提交于
Use setbits/clrbits macro instead of readl/writel function. (Suggested by Wolfgang) Signed-off-by: NInha Song <ideal.song@samsung.com> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Inha Song 提交于
This patch fixed that cfg value is set to wrong value. Because it didn't read the related register. Signed-off-by: NInha Song <ideal.song@samsung.com> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 07 2月, 2014 8 次提交
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由 Piotr Wilczek 提交于
This patch modifies envs to enable dual kernel boot - with separated DTB if the DTB file is loaded successfully; - with DTB apppended to uImage if DTB file is not found; This is neccesssary for backward compatibilty. Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Piotr Wilczek 提交于
This patch adds variables describing platform (soc, board, vendor) to default environment. Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Piotr Wilczek 提交于
This patch adds variables describing platform (soc, board, vendor) to default environment. Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Piotr Wilczek 提交于
This patch adds variables describing platform (soc, board, vendor) to default environment. Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: NPrzemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Piotr Wilczek 提交于
This patch adds variables describing platform (soc, board, vendor) to default environment. Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Cc: Mateusz Zalega <m.zalega@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Piotr Wilczek 提交于
This patch sets envs that describe board information. The following envs are set: soc_id, soc_rev, board_rev. Based on this information, if CONFIG_OF_LIBFDT is enabled, the 'fdtfile' env is set as: fdtfile=${soc_family}${soc_id}-${board}.dtb The generated envs are intenionally not saved to persistent storage. Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Piotr Wilczek 提交于
This patch adds s5p_cpu_rev. Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Piotr Wilczek 提交于
This patch enables to read cpu revision on Exynos CPU. Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 05 2月, 2014 4 次提交
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由 Inha Song 提交于
This patch fix the u-boot shell problem on TRATS2 board. - If hold the key while booting is in progress, white spaces are written in u-boot shell. Set Automatically clears after resetting Rx FIFO. Signed-off-by: NInha Song <ideal.song@samsung.com> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Acked-by: NLukasz Majewski <l.majewski@samsung.com> Tested-by: NLukasz Majewski <l.majewski@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Minkyu Kang 提交于
Because of the list of peripherals is not sequential, such a routine does not check for valid correctly. Error check will be done when call the exynos_pinmux_config function. Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com> Acked-by: NJaehoon Chung <jh80.chung@samsung.com> Acked-by: NRajeshwari Shinde <rajeshwari.s@samsung.com>
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由 Minkyu Kang 提交于
The value of PERIPH_ID_COUNT was wrong, and unnecessary. Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Minkyu Kang 提交于
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com> Acked-by: NRajehswari Shinde <rajeshwari.s@samsung.com>
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- 04 2月, 2014 22 次提交
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由 Jim Lin 提交于
Fix the timeout issue after running "bootp" command in U-Boot console. TXFIFOTHRES bits of TXFILLTUNING register should be set to 0x10 after a controller reset and before RUN bit is set (per technical reference manual). Signed-off-by: NJim Lin <jilin@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Tom Warren 提交于
These are the board files for Venice2 (Tegra124), plus the AS3722 PMIC files. PMIC init will be moved to pmic_common_init later. This builds/boots on Venice2, SPI/MMC/USB/I2C all work. Audio, display and WB/LP0 are not supported yet. Signed-off-by: NTom Warren <twarren@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Tom Warren 提交于
These are fairly complete, and near-clones of Tegra114 Venice, with an additional I2C port, and MMC address changes for Tegra124. Signed-off-by: NTom Warren <twarren@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Tom Warren 提交于
These files are used by both SPL and main U-Boot. Signed-off-by: NTom Warren <twarren@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Tom Warren 提交于
These files are for code that runs on the CPU (A15) on Tegra124 boards. At this time, there is no A15-specific code here. The warmboot/LP0 files aren't included as that code hasn't been ported yet. Signed-off-by: NTom Warren <twarren@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Tom Warren 提交于
This provides SPL support for Tegra124 boards - AVP early init, plus CPU (A15) init/jump to main U-Boot. Signed-off-by: NTom Warren <twarren@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Tom Warren 提交于
These headers define the Tegra124 hardware. Add them to the usual place. Add Tegra124 chip ID/SKU ID definitions to common headers. There's no real HW change on Tegra124 for 90% of the toys, so it might make sense for a future patch to unify some of the content of these files in a common location. Signed-off-by: NTom Warren <twarren@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
The reg property for node spi@7000d800 was wrong. Fix it to match the HW. This change was verified against the Linux kernel. Signed-off-by: NStephen Warren <swarren@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Tom Warren 提交于
__pinmux_nand() won't compile if PERIPH_ID_NDFLASH isn't defined. Prevent this from causing build problems on newer SoCs without NAND support (or without SW support for NAND yet), but preventing compilation unless the function will actually be used, i.e. when CONFIG_TEGRA_NAND is defined. Signed-off-by: NTom Warren <twarren@nvidia.com> [swarren, rewrote commit description, moved ifdef around whole function rather than just body] Signed-off-by: NStephen Warren <swarren@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
There's already an SoC-specific conditional in cpu.h to determine the PLLP rate. Define the CSITE clock rate inside the same conditional, so that we can remove a conditional from clock_enable_coresight(). This means one less place to update the code for new SoCs. Signed-off-by: NStephen Warren <swarren@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
This programming sequence is correct per Jimmy Zhang, and makes sense too! Signed-off-by: NStephen Warren <swarren@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
Pass just the partition ID to power_partition(), rather than also passing the partition's status register mask too. This makes it simpler to get call-sites correct, since they don't need to pass two different values that define the same thing and must match. Consequently, we can remove the mask definitions from pmc.h. Suggested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
Use a named constant for the PLL lock bit in enable_cpu_clocks(). Construct the complete value of pmc_pwrgate_toggle, rather than doing a read-modify-write; the register is simple enough and doesn't need to maintain state between operations. Signed-off-by: NStephen Warren <swarren@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
Tegra124's MMC controller is very similar to earlier SoC generations, and can be supported by the same driver. However, there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW. This patch updates the driver to support that new compatible value. That said, the HW differences are only relevant when enabling certain high-performance transfer modes. Since the driver is currently very simple and doesn't enable those modes, we don't actually need to address any of these HW differences in the code yet, hence the simple nature of this patch. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com> Tested-by: NThierry Reding <treding@nvidia.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Jimmy Zhang 提交于
Based on the Tegra TRM, the system clock (which is the AVP clock) can run up to 275MHz. On power on, the default sytem clock source is set to PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to 408MHz which is beyond system clock's upper limit. The fix is to set the system clock to CLK_M before initializing PLLP, and then switch back to PLLP_OUT4, which has an appropriate divider configured, after PLLP has been configured Implement this logic in new function tegra30_set_up_pllp(), which sets up PLLP and all PLLP_OUT* dividers, and handles the AVP clock switching. Remove the duplicate PLLP setup from pllx_set_rate() and adjust_pllp_out_freqs(). Signed-off-by: NJimmy Zhang <jimmzhang@nvidia.com> [swarren, significantly refactored the change] Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <treding@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
Tegra114 and later's PMC module removes the pwrgate_timer_on register and replaces it with a clamp_status register. Adjust pmc.h to reflect this, and update any code affected by the change. The cpu.c change in this patch was extracted from a much larger patch by Jimmy Zhang. The pmc.h change was written from scratch, but inspired by related changes made by Tom Warren. There could well be other differences in the PMC register set for chips after Tegra20/30. However, they don't affect the code in U-Boot at present, so I haven't attempted an exhaustive update of pmc.h. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <treding@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Tom Warren 提交于
Some clock sources have 3-bit muxes in bits 31:29. Implement core support for this mux field. Signed-off-by: NTom Warren <twarren@nvidia.com> [swarren, extracted from a larger patch by Tom] Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <treding@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
Since all code that sets or interprets MASK_BITS_* now uses the enums to define/compare the values, there is no need for MASK_BITS_* to have a specific integer value. In fact, having a specific integer value may encourage people to hard-code those values, or interpret the values in incorrect ways. As such, remove the logic that assigns a specific value to the enum values in order to make it completely clear that it's just an enum, not something that directly represents some integer value. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <treding@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
Not all code that set or interpreted "mux_bits" was using the named macros, but rather some was simply using hard-coded integer constants. This makes it hard to determine which pieces of code are affected by changes to those constants. Replace the integer constants with the equivalent macro definitions so that everything is nicely tied together. Note that I'm not convinced all the code was using the correct integer constants, and hence I'm not convinced that all the code is now using the desired macros. However, this change is a purely mechanical replacement and should have no functional change. Fixing any bugs will come later, separately. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <treding@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
OUT_CLK_SOURCE_ are currently named after the number of bits the mask they represent includes. However, bit count is not the only possible variable; bit position may also vary. Rename OUT_CLK_SOURCE_ to OUT_CLK_SOURCE_31_30_ and OUT_CLK_SOURCE4_ to OUT_CLK_SOURCE_31_28 to more completely describe exactly what they represent, without having to go look up the definitions. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <treding@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
The only place where the MASK_BITS_* values are used is in adjust_periph_pll(), which interprets the value 4 (old MASK_BITS_29_28, new MASK_BITS_31_28) as being associated with mask OUT_CLK_SOURCE4_MASK, i.e. bits 31:28. Rename the MASK_BITS_ macro to reflect how it's actually implemented. Note that no Tegra clock register actually uses all of bits 31:28 as the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in those cases, nothing is stored in the bits above the mux field, so it's safe to pretend that the mux field extends all the way to the end of the register. As such, the U-Boot clock driver is currently a bit lazy, and doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps them all together and pretends they're all 31:28. This patch doesn't cause this issue; it was pre-existing. Hopefully, future patches will clean this up. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <treding@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Tom Warren 提交于
The enum used to define the set of register bits used to represent a clock's input mux, MUX_BITS_*, is defined separately for each SoC at present. Move this definition to a common location to ease fixing up some issues with the definition, and the code that uses it. Signed-off-by: NTom Warren <twarren@nvidia.com> [swarren, extracted from a larger patch by Tom] Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <treding@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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