Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NSrikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: NDejan Minic <minic@freescale.com>
Signed-off-by: NJason Jin <Jason.jin@freescale.com>
Signed-off-by: NDave Liu <daveliu@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

The L2_INIT_RAM option was unused, and recent changes to the TLB code
meant that the INIT_RAM TLBs weren't being cleared out.  In order to reduce
the amount of mapped space attached to nothing, we change things so the TLBs
get cleared.
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The fake flash bank was generating errors for anyone who didn't have a
PromJET hooked up to the board.  As that constitutes the vast majority of
users, we remove it.
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Add support for using a PCIe ATI Video card on PCIe2.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The 8544 DS doesn't have any cacheable Local Bus memories set up.  By mapping
space for some anyway, we were allowing speculative loads into unmapped space,
which would cause an exception (annoying, even if ultimately harmless).
Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the
problem.
Signed-off-by: NAndy Fleming <afleming@freescale.com>

A number of board ports have empty version of board_early_init_f
for no reason since we control its via CONFIG_BOARD_EARLY_INIT_F.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

* Enable flash progress
* remove CLEAR_LAW0 since we dont really use it
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Remove unused and unconfigured DDR test code from FSL 85xx boards.
Besides, other common code exists.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This patch removes the unknown flash message information:
'## Unknown FLASH on Bank 1 - Size = 0xdeadbeef = -286261248 MB'
This unknown flash message is caused by PromJet.
Some of the board user is unhappy with this information.
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

When we go to 36-bit physical addresses we need to keep the concept of
the physical CCSRBAR address seperate from the virtual one.

For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Now that all boards have been converted, remove old config code and the
config option for the new style.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Either use the standard defines in asm/cache.h or grab the information
at runtime from the L1CFG SPR.

Also, minor cleanup in cache.h to make the code a bit more readable.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

On the MPC85xx boards that have PCIe enable the PCIe errata fix.
(MPC8544DS, MPC8548CDS, MPC8568MDS).
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

* Enabled CONFIG_CMD_ELF
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

* Removed HAS_ETH2/HAS_ETH3 - MPC8544 only has TSEC1/2
* Removed some misc environment setup
* Moved to using fdtfile & fdtaddr as fdt env var names
* Enabled CONFIG_CMDLINE_EDITING
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Updated the MPC8544DS config to use libfdt and assume use of aliases for
ethernet, pci, and serial for the various fixups that are done.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Basically, refactor the CFG_PIXIS_VBOOT_MASK values
into the separate board config files.
Signed-off-by: NJason Jin <Jason.jin@freescale.com>
Signed-off-by: NJon Loeliger <jdl@freescale.com>

Basically, refactor the CFG_PIXIS_VBOOT_MASK values
into the separate board config files.
Signed-off-by: NJason Jin <Jason.jin@freescale.com>
Signed-off-by: NJon Loeliger <jdl@freescale.com>

The RTC on the M1575 ULI chipset requires a dummy read before
we are able to talk to the RTC.  We accomplish this by adding a
second memory region to the PHB the ULI is on and read from it.

The second region is added to maintain compatiabilty with Linux's
view of the PCI memory map.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

if a board/$(VENDOR)/common/Makefile exists, build it.

also add the first such case, board/freescale/common/Makefile, to
handle building board-shared EEPROM, PIXIS, and MDS-PIB code, as
dictated by board configuration.

thusly get rid of alternate build dir errors such as:

FATAL: can't create /work/wd/tmp/u-boot-ppc/board/freescale/mpc8360emds/../common/pq-mds-pib.o: No such file or directory

by putting the common/ mkdir command in its proper place (the common
Makefile). Common bits from existing individual board Makefiles have
been removed.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

and make some minor corrections to the FDT part of the README.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

The PCIe bus that the ULI M1575 is connected to has no possible way of
needing more than the fixed amount of IO & Memory space needed by the ULI.

So make it use far less IO & memory space and have it use the shared LAW.  This
free's up a LAW for PCIe1 IO space.  Also reduce the amount of IO space needed
by each bus.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

It looks like we had a merge issue that duplicated a bit of code
in ft_board_setup.  Also, we need to set CONFIG_HAS_ETH0 to get
the MAC address properly set in the device tree on boot for TSEC1
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The tsec_info structure and array has a "flags" field for each
ethernet controller.  This field is the only reason there are
settings.  Switch to defining TSECn_FLAGS for each controller
in the config header, and we can greatly simplify the array, and
also simplify the addition of future boards.
Signed-off-by: NAndy Fleming <afleming@freescale.com>

PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address.

Enable LBC and ECM errors and clear error registers.

Add tftpflash env var to get uboot from tftp server and flash it.

Add pci/pcie convenience env vars to display register space:
  "run pcie3regs" to see all pcie3 ccsr registers
  "run pcie3cfg" to see all cfg registers
Whitespace cleanup and MPC8544DS.h

Enable CONFIG_INTERRUPTS.
Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com>
Acked-by: NAndy Fleming <afleming@freescale.com>

Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h
used to be included but CONFIG_BOOTP_MASK was not defined.

Remove lingering references to CFG_CMD_* symbols.
Signed-off-by: NJon Loeliger <jdl@freescale.com>

Signed-off-by: NJon Loeliger <jdl@freescale.com>

For all practical u-boot purposes, TSECs don't differ throughout the
mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: NJon Loeliger <jdl@freescale.com>