- 22 7月, 2020 21 次提交
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由 Jagan Teki 提交于
This patch adds support to enable PCIe for RockPI N10. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Jagan Teki 提交于
This patch adds support to enable HDMI out for N10 and N8 combinations SBCs. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Jagan Teki 提交于
Radxa dalang carrier board has 2x USB 2.0 and 1x USB 3.0 ports. This patch adds support to enable all these USB ports for N10 and N8 combinations SBCs. Note that the USB 3.0 port on RockPI N8 combination works as USB 2.0 OTG since it is driven from RK3288. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Jagan Teki 提交于
rk3288 and rk3288w have a usb host0 ohci controller. Although rk3288 ohci doesn't actually work on hardware, but rk3288w ohci can work well. So add usb host0 ohci node in rk3288 dtsi and the quirk in ohci platform driver will disable ohci on rk3288. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Suniel Mahesh 提交于
This sync has changes required to use HDMI CEC pin in U-Boot. Sync dts from linux v5.8-rc5 commit: "ARM: dts: rockchip: define the two possible rk3288 CEC pins" (sha1: 838980dd04e994bf81cf104fa01ae60802146b39) Signed-off-by: NSuniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
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由 Jagan Teki 提交于
Sync ROCKPi N8/N10 dts(i) changes from Linux. commit <afd9eb880414> ("ARM: dts: rockchip: Add Radxa Rock Pi N8 initial support") Signed-off-by: NSuniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
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由 Jagan Teki 提交于
reset cause is a generic functionality based on the soc cru registers in rockchip. This can be used for printing the cause of reset in cpuinfo or some other place where reset cause is needed. Other than cpuinfo, reset cause can also be using during bootcount for checking the specific reset cause and glow the led based on the reset cause. So, let's separate the reset cause code from cpuinfo, and add a check to build it for rk3399, rk3288 since these two soc are supporting reset cause as of now. Tested-by: NSuniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Jagan Teki 提交于
reset reason can be used several stages of U-Boot bootloader like SPL, U-Boot proper based on the requirements. Clearing the status register end of get_reset_cause will end up showing the wrong reset cause when it read the second time. For example, if board resets, SPL reads the reset status as RST whereas U-Boot proper reads the status as POR. However, based on the latest testing clearing reset status won't be required for determine the last reset cause or following resets. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
There is no need for board_early_init_f() in TPL, anything like this should goes to SPL. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Jagan Teki 提交于
Add weak led_setup() so that board which has an uncommon led setup code that can make use of custom implementation. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Jagan Teki 提交于
The new rk3288 revision rk3288w has some changes with respect to legacy rk3288 like hclk_vio in cru and usb host0 ohci. Linux clock driver already handle this via rockchip,rk3288w-cru compatible. USB ohci host can enable via dts for rk3288w based boards. So, add fdt board setup code to update cru compatible with rk3288w-cru compatible if the SOC revision is RK3288W. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Jagan Teki 提交于
Rockchip SoC's has a new revision chip for rk3288 SoCs. RK3288 has a new revision chip called RK3288W which is similar but different hclk_vio clock and fixed OHCI host. Add common Rockchip SoC detection helper to support this rk3288w detection. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Jagan Teki 提交于
Rock PI 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enabled GPIO pin change compared to 4B, 4C. So, add or enable difference nodes/properties in 4C dts by including common dtsi. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Jagan Teki 提交于
Rock PI 4 has 3 variants of hardware platforms called RockPI 4A, 4B, and 4C. - Rock PI 4A has no Wif/BT. - Rock PI 4B has AP6256 Wifi/BT, PoE. - Rock PI 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enable GPIO pin change compared to 4B, 4C So move common nodes, properties into dtsi file and include on respective variant dts files. Use 4B dts into default rock-pi-4 defconfig until we find any solution for dynamic detection of these variants. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Alex Bee 提交于
Currently 2.5 GB is calculated as DRAM size for a 1 GB RK322x board if CONFIG_SPL_OPTEE is set. This is troublesome when booting a linux kernel since this size will be injected in FDT of the kernel. gd->bd->bi_dram[0].start (which is basically CONFIG_SYS_SDRAM_BASE) must not be taken into consideration for calculation of second bank size, since this offset is already included in calculation of "top". After applying this patch 992 MB (1024 MB - 32 MB reserved for optee-os) is correctly calculated and has also been verified on 2 GB boards. Signed-off-by: NAlex Bee <knaerzche@gmail.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
The empty function define should not be in the header file, or else the build will error with function multi definition after CONFIG_RAM_ROCKCHIP_DEBUG is disabled. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Johannes Krottmayer 提交于
Add U-Boot SPI Flash support for the PINE64 Rock64 board Signed-off-by: NJohannes Krottmayer <krjdev@gmail.com> Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Johannes Krottmayer 提交于
Add U-Boot SPI support for the RK3328 Signed-off-by: NJohannes Krottmayer <krjdev@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com> (fix checkpatch error for code ident) Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Heiko Stuebner 提交于
Also known as Odroid Go Advance but named Go2 internally by the vendor it seems. Signed-off-by: NHeiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Heiko Stuebner 提交于
Get the devicetree from mainline Linux and include it for U-Boot uses. Signed-off-by: NHeiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Heiko Stuebner 提交于
The rk3326 is just a trimmed down px30 from a software perspective, so the mainline rk3326 dtsi also ist just a tiny addition. Signed-off-by: NHeiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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- 17 7月, 2020 19 次提交
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由 Masahiro Yamada 提交于
Some code was not converted by coccinelle, somehow. I manually fixed up the remaining, and comments, README docs. Signed-off-by: NMasahiro Yamada <masahiroy@kernel.org> [trini: Add arch/arm/mach-davinci/include/mach/sdmmc_defs.h and include/fdt_support.h] Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Masahiro Yamada 提交于
The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: NMasahiro Yamada <masahiroy@kernel.org>
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由 Patrick Delaunay 提交于
This converts the following to Kconfig: CONFIG_ARMV7_PSCI_1_0 CONFIG_ARMV7_PSCI_0_2 Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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由 Simon Glass 提交于
This should ideally be used by all x86 boards in U-Boot. Enable it by default. If some boards don't use it, the cost is small. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
This function sounds like something that is called when U-Boot is about to jump to Linux. In fact it is an init function. Rename it to reduce confusion. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
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由 Simon Glass 提交于
Currently U-Boot implements version 2 but reports version 4. Correct it. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
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由 Simon Glass 提交于
This function does not exist anymore. Drop it from the header file. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
The comment here applies only to FSP1, so update it. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
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由 Simon Glass 提交于
At present this information is used to locate and parse the tables but is not stored. Store it so that we can display it to the user, e.g. with the 'bdinfo' command. Note that now the GD_FLG_SKIP_LL_INIT flag is set in get_coreboot_info(), so it is always set when booting from coreboot. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
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由 Simon Glass 提交于
Update this code to calculate the address to use, rather than hard-coding it. Obtain the requested stack size from the FSP. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
If there is MRC information we should run FSP-M with a different boot_mode flag since it is supposed to do a 'fast path' through the memory init. Fix this. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Writing tables is currently pretty opaque. Add a bit of debugging to the process so we can see what tables are written and where they start/end in memory. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
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由 Simon Glass 提交于
The FSP-S changes the ITSS priorities. The code that tries to save it before running FSP-S and restore it afterwards does not work as U-Boot relocates in between the save and restore. This means that the driver data saved before relocation is lost and the new driver just sees zeroes. Fix this by allocating space in the relocated memory for the ITSS data. Save it there and access it from the driver after relocation. This fixes interrupt handling on coral. Also drop the log_msg_ret() in irq_first_device_type() since this function can be called speculatively in places where we are not sure if there is an interrupt controller of that type. The resulting log errors are confusing when there is no error. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
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由 Simon Glass 提交于
This binding currently has a flags cell but it is not used. Make use of it to create ACPI tables for interrupts. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
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由 Simon Glass 提交于
This confuses Linux's PCI probing so needs to be hidden when booting Linux. Add a remove() method to handle this. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
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由 Simon Glass 提交于
Add support for this new method in the driver and in the fsp-s setup. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
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由 Simon Glass 提交于
Use the new binman memory-mapping function to access the VBT, to simplify the code. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Generation of this table can fail, so update the function to return an error code. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
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由 Simon Glass 提交于
This is in the device tree now, so drop the unnecessary field here. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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