Commit f4dc714a ("arm64: Turn u-boot.bin back into an ELF file after
relocate-rela")
introduce REMAKE_ELF option to recreate u-boot.elf from u-boot ->
u-boot.bin + DT -> u-boot.elf.

The best is to ilustrate it from make V=1 output
  cat u-boot-nodtb.bin dts/dt.dtb > u-boot-dtb.bin
  cp u-boot-dtb.bin u-boot.bin
aarch64-linux-gnu-objcopy -I binary -B aarch64 -O elf64-littleaarch64  u-boot.bin u-boot-elf.o
  aarch64-linux-gnu-ld.bfd u-boot-elf.o -o u-boot.elf --defsym="_start"=0x8000000 -Ttext=0x8000000

Last command has no explicit linker script passed that's why toolchain
internal linker script is used.
In Binutils 2.32 case it contains SIZEOF_HEADERS symbol which has changed
behavior by commit
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=64029e93683a266c38d19789e780f3748bd6a188
which result in situation that program headers has changed from
(xilinx_zynqmp_mini_defconfig)

Program Headers:
  Type           Offset             VirtAddr           PhysAddr
                 FileSiz            MemSiz              Flags  Align
  LOAD           0x0000000000010000 0x00000000fffc0000 0x00000000fffc0000
                 0x0000000000018918 0x0000000000018918  RW     0x10000

to

Program Headers:
  Type           Offset             VirtAddr           PhysAddr
                 FileSiz            MemSiz              Flags  Align
  LOAD           0x0000000000000000 0x00000000fffb0000 0x00000000fffb0000
                 0x0000000000028918 0x0000000000028918  RW     0x10000

Xilinx tools like XSDB or Bootgen are using program headers for loading ELF
to the right location and by above binutils change ELF is loaded to
incorrect location.

The patch is explicitly use u-boot-elf.lds (just cat now) for u-boot.elf
recreation which is called when REMAKE_ELF is setup.
By purpose u-boot-elf.lds doesn't contain OUTPUT_FORMAT/OUTPUT_ARCH to be
able to use by all archs.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-By: NÁlvaro Fernández Rojas <noltari@gmail.com>

When generating the MAC address based on the boards serial number
the last digit was overwritten with the null termination. That way
boards with serial numbers close to each other would use the same
MAC address.
Signed-off-by: NJan-Christoph Tebbe <Jan-Christoph.Tebbe@ithinx.io>

Commit cf8dcc5d ("common: spl_fit: Default to IH_OS_U_BOOT if
FIT_IMAGE_TINY enabled") is not correct, it will append fdt to each loadable
image. Actually when using TINY FIT, the first loadable image is thought as
u-boot and already have fdt appended.
Signed-off-by: NYe Li <ye.li@nxp.com>
Tested-by: NFabio Estevam <festevam@gmail.com>

- fix for MMIO window size (Tudor Ambarus)

- rockchip RK3399 HDMI output fix

The default resolution for rockchip display is 1920x1080
which failed to work on 4K HDMI out displays on rk3399.

So, mark the default resolution as 3480x2160 for rk3399
HDMI out.

This would work all the hdmi display resolutions till
4K.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NPeter Robinson <pbrobinson@gmail.com>

Enable config options and console setting to respective
rk3399 board for HDMI output.

Boards supported and tested on this patch are:
- NanoPc T4
- NanoPi M4
- NanoPi Neo4
- ROC-RK3399-PC
- Rock960

Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Tested-by: NPeter Robinson <pbrobinson@gmail.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Enable pre console buffer for rk3399 platform.

This would help to capture the console messages prior to
the console being initialised. Enabling this would help
to capture all the console messages on video output source
like HDMI. So we can find the full console messages of
U-Boot proper on HDMI display when enabled it for RK3399
platform boards.

Buffer address used for pre console is 0x0f200000 which is
ram base plus 240MiB. right now the Allwinner SoC is using
similar computation.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NPeter Robinson <pbrobinson@gmail.com>

VOP display endpoint pipeline configuration differs
between rk3288 vs rk3399.

These VOP pipeline configuration depends on how the
different display interfaces connected in sequence to
IN and OUT ports like for,

RK3288:

vopb_out: port {
	#address-cells = <1>;
	#size-cells = <0>;
	vopb_out_edp: endpoint@0 {
		reg = <0>;
		remote-endpoint = <&edp_in_vopb>;
	};
	vopb_out_hdmi: endpoint@1 {
		reg = <1>;
                remote-endpoint = <&hdmi_in_vopb>;
        };
        vopb_out_lvds: endpoint@2 {
                reg = <2>;
                remote-endpoint = <&lvds_in_vopb>;
        };
        vopb_out_mipi: endpoint@3 {
                reg = <3>;
                remote-endpoint = <&mipi_in_vopb>;
        };
};

RK3399:

vopb_out: port {
         #address-cells = <1>;
         #size-cells = <0>;
         vopb_out_edp: endpoint@0 {
                reg = <0>;
                remote-endpoint = <&edp_in_vopb>;
         };
         vopb_out_mipi: endpoint@1 {
                reg = <1>;
                remote-endpoint = <&mipi_in_vopb>;
         };
         vopb_out_hdmi: endpoint@2 {
                reg = <2>;
                remote-endpoint = <&hdmi_in_vopb>;
         };
         vopb_out_mipi1: endpoint@3 {
                reg = <3>;
                remote-endpoint = <&mipi1_in_vopb>;
         };
         vopb_out_dp: endpoint@4 {
                reg = <4>;
                remote-endpoint = <&dp_in_vopb>;
         };
};

here, HDMI interface has endpoint 1 in rk3288 and 2 in rk3399.

The rockchip vop driver often depends on this determined endpoint
number and stored in vop_mode. So based on this vop_mode the bpp
and pin polarity would configure on detected display interface.

Since, the existing driver using rk3288 vop mode settings enabling
the same will result wrong display interface configuration for rk3399.

Add the patch for fixing these vop modes for rk3399.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NPeter Robinson <pbrobinson@gmail.com>

During vidconsole probe, the device probe will try to
check whether the assigned clocks on that video console
node is initialized or not? and return an error if not.

But, unlike Linux U-Boot won't require to handle these
vopl assigned-clocks since core clocks are enough to
handle the video out to process.

So, mark them as empty in set_rate to satisfy clk_set_defaults
so-that probe happened properly.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NPeter Robinson <pbrobinson@gmail.com>

This feature should not be enabled in release but can be useful for
developers who need to monitor register accesses at some specific places.

Helped me identify a bug in u-boot, by comparing the register accesses
from the u-boot driver with the ones from its linux variant.
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>
[jagan: use 16 bit array with tmp variable]
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>

The sama5d2 QSPI controller memory space is limited to 128MB:
0x9000_00000-0x9800_00000/0XD000_0000--0XD800_0000.

There are nor flashes that are bigger in size than the memory size
supported by the controller: Micron MT25QL02G (256 MB).

Check if the address exceeds the MMIO window size. An improvement
would be to add support for regular SPI mode and fall back to it
when the flash memories overrun the controller's memory space.

Fixes: 24c8ff46 ("spi: Add Atmel QuadSPI driver")
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>

Vboot vulnerability fix

- Fix device tree of Avenger96 board from Arrow Electronics and add
  compatibility with stm32mp15_dhcom_basic_defconfig

We don't need 5KB to test things out. A smaller size makes it easier to
look at the FIT with fdtdump.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This code is repeated so move it into a function with a parameter.
Signed-off-by: NSimon Glass <sjg@chromium.org>

These are used in multiple places so update them to use a shared #define.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NPhilippe Reynes <philippe.reynes@softathome.com>

Fix various minor things noticed by pylint.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Fix some long lines and comments. Use a distinct name for the
'required key' test.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This tool always verifies the default configuration. It is useful to be
able to verify a specific one. Add a command-line flag for this and plumb
the logic through.
Signed-off-by: NSimon Glass <sjg@chromium.org>

At present bootm_host_load_images() is passed the configuration that has
been verified, but ignores it and just uses the default configuration.
This may not be the same.

Update this function to use the selected configuration.
Signed-off-by: NSimon Glass <sjg@chromium.org>

It is currently possible to use a different configuration's signature and
thus bypass the configuration check. Make sure that the configuration node
that was hashed matches the one being checked, to catch this problem.

Also add a proper function comment to fit_config_check_sig() and make it
static.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This test is actually made up of five separate tests. Split them out so
that they appear as separate tests.

Unfortunately this restarts U-Boot multiple times which adds about a
second to the already-long vboot test, about 8 seconds total on my
machine. We could add a special 'teardown' test afterwards but if the
tests are executed out of order that would not work.

Changing test_vboot into a class causes it not to be discovered and makes
it different from all other tests.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add a check to make sure that it is not possible to add a new
configuration and use the hashed nodes and hash of another configuration.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This tool only uses the last -k parameter provided. Drop the earlier one
since it has no effect.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This function only returns an error message sometimes. Update it to always
return an error message if one is available. This makes it easier to see
what went wrong.
Signed-off-by: NSimon Glass <sjg@chromium.org>

It is useful to be a little more specific about what is being checked.
Update a few messages to help with this.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This should mention that conf_uname can be NULL and should be in the
header file. Fix this.
Signed-off-by: NSimon Glass <sjg@chromium.org>

The core and vdd PMIC buck regulators were misconfigured, which caused
instability of the board and malfunction of high-speed interfaces, like
the RGMII. Configure the PMIC correctly to repair these problems. Also,
model the missing Enpirion EP53A8LQI on the DHCOR SoM as a fixed regulator.
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>

Add PHY reset GPIO on AV96 ethernet PHY.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>

The AV96 RGMII uses different pinmux for ETH_RGMII_TXD0, ETH_RGMII_RXD2
and ETH_RGMII_TX_CTL. Use the correct pinmux to make ethernet operational.
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>

Add another mux option for DWMAC RGMII, this is used on AV96 board.
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>

The board has an EEPROM on the same I2C bus as PMIC, at address 0x53.
The EEPROM contains the board MAC address.
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Change-Id: I340a0675c11e4599968b2e3ef0515fb8da8d7b42

Use DT /aliases node to establish a stable phandle to the configuration
EEPROM. This permits the configuration EEPROM to be moved e.g. to a
different address or a different bus. Adjust the board code to handle
new phandle lookup.
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>

The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it
into the DT.
Signed-off-by: NMarek Vasut <marex@denx.de>
Reviewed-by: NPatrick Delaunay <patrick.delaunay@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Change-Id: Ia7c454c496f50e3fc4851ec1154f3641c416e98e

The eMMC uses different pinmux for the top four data lines, use such
a pinmux, otherwise it takes a very long time until the test for 8bit
operation times out. And this is the correct pinmux per schematic too.
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>

Add another mux option for SDMMC2 pins 4..7, this is used on AV96 board.
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>

The SD uses different pinmux for the D123DIRline, use such a pinmux,
otherwise there is a pinmux collision on the AV96. Add missing SD
voltage regulator switch and enable SDR104 operation.
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>

Add another mux option for SDMMC1 direction pins, in particular
SDMMC1_D123DIR, this is used on AV96 board.
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>

The sdmmc1_dir_pins_a: sdmmc1-dir-0 layout changed in commit 35a54d41
("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") such that pins{};
became pins1{};pins2{};, however the SPL extras were not updated to reflect
that change. Fix this.

This fixes booting from SD1 X9 slot on the AV96 board.
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NPatrick Delaunay <patrick.delaunay@st.com>
Fixes: 35a54d41 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4")
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>