We have flipped CONFIG_SPL_DISABLE_OF_CONTROL.  We have cleansing
devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear
away the ugly logic in include/fdtdec.h:

 #ifdef CONFIG_OF_CONTROL
 # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL)
 #  define OF_CONTROL 0
 # else
 #  define OF_CONTROL 1
 # endif
 #else
 # define OF_CONTROL 0
 #endif

Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute.  It refers to
CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for
SPL.

Also, we no longer have to cancel CONFIG_OF_CONTROL in
include/config_uncmd_spl.h and scripts/Makefile.spl.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Enable the mtdparts command and related options to make support
for SPI NOR MTD useful in any way. With the mtdparts command in
place, it is possible to use partition of the SPI NOR in U-Boot.
Signed-off-by: NMarek Vasut <marex@denx.de>

This is needed to access broken (read: Micron) SPI flashes which
are larger than 16 MiB and don't correctly support 4-byte addressing.
Signed-off-by: NMarek Vasut <marex@denx.de>

We do not need full MTD support in the SPL build, it only adds size
and is not usable in any way. Exclude it.
Signed-off-by: NMarek Vasut <marex@denx.de>

There is no need to disable support for partitions in the SPL,
we can support partitions in SPL perfectly well. This is likely
some remnant from old times, so just remove this configuration
option.

Moreover, the CRC32 chunk size doesn't have to be adjusted anymore,
since both the GD and malloc area are in RAM by the time this CRC
check can be used and there's plenty of space. Zap this abomination
as well.
Signed-off-by: NMarek Vasut <marex@denx.de>

Now that the SPL structure is organised such that it matches the
U-Boot's SPL design, it is possible to use the option of relocating
GD to RAM. And since we have GD in RAM, move malloc area to RAM as
well. We point the malloc base pointer 1 MiB past U-Boot's load
address. We use simple malloc for SPL because it is 3kiB smaller
in terms of code size than regular malloc which was used thus far.
Signed-off-by: NMarek Vasut <marex@denx.de>

setenv an environment variable called "bootmode" , which contains the
board boot mode. This can be in turn used in scripts to determine from
where to load kernel and such.
Signed-off-by: NMarek Vasut <marex@denx.de>

Add code and configuration options to support booting from QSPI NOR.
Enable support for booting from QSPI NOR.
Signed-off-by: NMarek Vasut <marex@denx.de>

Add code and configuration options to support booting from RAW
SD/MMC card as well as for ext4/vfat filesystems. Enable support
for booting from SD/MMC card, but don't enable the filesystem
support just yet to retain compatibility with old SoCFPGA card
format.
Signed-off-by: NMarek Vasut <marex@denx.de>

Remove the custom SPL linker script, use the generic one instead.
The custom script doesn't bring in anything new and is only burden
to maintain.
Signed-off-by: NMarek Vasut <marex@denx.de>

The code in spl_board_init() should have been in board_init_f()
from the beginning, since it is code which configures system and
then starts DRAM. Thus, it cannot be in spl_board_init(), which
is called from board_init_r() , which already expects a working
DRAM.
Signed-off-by: NMarek Vasut <marex@denx.de>

Enable the Altera SDRAM driver for the SoCFPGA platform.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: NMarek Vasut <marex@denx.de>

This introduces a coherent scheme for naming USB download gadget and functions
config options. The download USB gadget config option is moved to
CONFIG_USB_GADGET_DOWNLOAD for better consistency with other gadgets and each
function's config option is moved to a CONFIG_USB_FUNCTION_ prefix.
Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>
Tested-by: NLukasz Majewski <l.majewski@samsung.com>

Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)

Some archs/boards specify their own default by pre-defining the config
which causes the Kconfig system to mix up the order of the configs in
the defconfigs... This will cause merge pain if allowed to proliferate.

Remove the configs that behave this way from the archs.

A few configs still remain, but that is because they only exist as
defaults and do not have a proper Kconfig entry. Those appear to be:

SPIFLASH
DISPLAY_BOARDINFO
Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com>
[trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates,
drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM]
Signed-off-by: NTom Rini <trini@konsulko.com>

CONFIG_NET_MULTI is not used anywhere and thus can safely be removed
from the configs.
Acked-by: NMarek Vasut <marex@denx.de>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NLars Poeschel <poeschel@lemonage.de>

Replace CONFIG_SOCFPGA with CONFIG_ARCH_SOCFPGA.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Our recent trend is to collect SoC files into arch/arm/mach-(SOC).
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

We need to adjust the SYS_INIT_RAM_SIZE to have room for the
SPL_MALLOC_SIZE.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

The Cyclone5 SoCFPGA has 64KB of OCRAM for SPL use.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

Move this to Kconfig and clean up board config files that use it. Also
rename it to CONFIG_ETH_DESIGNWARE to fit with the naming that exists
in drivers/net/Kconfig.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Version 1:
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Zap this unused empty function, no point in having it.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Acked-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: NPavel Machek <pavel@denx.de>
Reviewed-by: NStefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>

Since all boards now have a DT, instead of hard-coding the board
name into the U-Boot binary, read the board name from DT "model"
property.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: NPavel Machek <pavel@denx.de>
Acked-by: NStefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>

Remove driver model CONFIGs from the board config headers and use Kconfig
instead.
Signed-off-by: NSimon Glass <sjg@chromium.org>

The current current watchdog timeout of 12 seconds is a bit small for
booting into Linux, especially when using a NFS based rootfs. So lets
change this timeout to a more defensive value of 30 seconds.

Also we now call the hw_watchdog_init() function so that we override
the value already configured from the Preloader.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>

Remove the now unnecessary clocking info from the SoCFPGA
config header. As this info in now used directly in the SPI driver
itself.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: NPavel Machek <pavel@denx.de>

Enable support for the DW master SPI controller in the config header
for the SoCFPGA. This controller can only be enabled, if DT support
is enabled.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>

With this driver enabled for SoCFPGA, access to SPI NOR flash is
supported.

The configuration (page size, timing info) will be taken from the
DT. See socrates as an example.

This QSPI supports depends on DT. So QSPI is only enabled if
CONFIG_OF_CONTROL is defined (see socfpga_socrates_defconfig).
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

Some (not all) of ARMv7 boards define CONFIG_ARMV7, which is useless.
Besides, it is never referenced.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Add example of an USB UDC configuration with DFU and UMS.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Acked-by: NPavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: NLukasz Majewski <l.majewski@samsung.com>

Add example config file entry for the Altera SPI controller. This SPI
controller can also, under special conditions, be used to operate the
EPCS/EPCQ SPI NOR.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

This patch adds I2C support for the SoCFPGA. Using the designware I2C
controller driver. It supports all 4 I2C busses on the SoCFPGA.

The designware I2C driver has now been converted to the
CONFIG_SYS_I2C framework. So lets enable it on SoCFPGA.

Tested on SoCrates.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Heiko Schocher <hs@denx.de>

Add example configuration stub for the DWC2 USB controller.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Pavel Machek <pavel@denx.de>

Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h
contained various ad-hoc symbols, zap those symbols as well and rework the
board configuration a little so it doesn't depend on them.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: NPavel Machek <pavel@denx.de>

Move this initialization code to proper place. The misc_init_r()
function is called way too late and the platform initialization
code should be executed much earlier.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: NPavel Machek <pavel@denx.de>

Split the SoCFPGA configuration into SoC-specific part which is
common for all boards (socfpga_cyclone5_common.h) and a board
specific part. There is currently only one board, which is the
generic SoCFPGA board (socfpga_cyclone5.h), but there are more
to come.

This is necessary due to various features of the boards, which
unfortunatelly cannot be autodetected.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: NPavel Machek <pavel@denx.de>

Reorganize and cleanup the configuration file for SoCFPGA. There
is no functional change after this cleanup. This was necessary,
since the file was a wild mess and it was impossible to make sense
of it's content, let alone change something without breaking some
other thing. This patch puts the contents on par with regular U-Boot
standards.

Also remove unused preprocessor symbols CONFIG_SINGLE_BOOTOADER
and CONFIG_USE_IRQ, which is undefined by default. Finally, do
logical reordering of the defines in the file so it's much more
readable. The reordering was also necessary for the splitting
as the initial one was messy.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit.
Enable the bootz command as zImage is used instead uImage.
Signed-off-by: NChin Liang See <clsee@altera.com>
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: NPavel Machek <pavel@denx.de>

Enable the DesignWare MMC controller driver support
for SOCFPGA Cyclone5 dev kit
Signed-off-by: NChin Liang See <clsee@altera.com>
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: NPavel Machek <pavel@denx.de>

Enable the PL310 L2 cache controller support for the SoCFPGA.
With the cache related issues resolved, this is safe to be done.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: NPavel Machek <pavel@denx.de>