To squash that nasty warning message and make better use of the newly
gained OF_CONTROL feature, let's convert the calxedagmac driver to the
"new" driver model.
The conversion is pretty straight forward, mostly just adjusting the
use of the involved data structures.
The only actual change is the required split of the receive routine into
a receive and free_pkt part.
Also this allows us to get rid of the hardcoded platform information and
explicit init calls.

This also uses the opportunity to wrap the code decoding the MMIO
register base address, to make it safe for using PHYS_64BIT later.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NRamon Fried <rfried.dev@gmail.com>

All Calxeda machines are actually a poster book example of device tree
usage: the DT is loaded from flash by the management processor into
DRAM, the memory node is populated with the detected DRAM size and this
DT is then handed over to the kernel.
So it's a shame that U-Boot didn't participate in this chain, but
fortunately this is easy to fix:

Define CONFIG_OF_CONTROL and CONFIG_OF_BOARD, and provide a trivial
function to tell U-Boot about the (fixed) location of the DTB in DRAM.
Then enable DM_SERIAL, to let the PL011 driver pick up the UART platform
data from the DT. Also define AHCI, to bring this driver into the driver
model world as well.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>

So far on Highbank/Midway machines U-Boot only ever uses 512MB of DRAM,
even though the machines have typically 4GB and 8GB, respectively.
That means that so far we didn't need an extra limit for placing the DTB
and initrd, as the 512MB are lower than the kernel's limit ("lowmem",
typically 768MB).

With U-Boot now needing to learn about the actual memory size (to
correctly populate the EFI memory map), it might relocate fdt and initrd
to the end of DRAM, which is out of reach of the kernel.

So add limiting values to the fdt_high and initrd_high environment
variables, to prevent U-Boot from using too high addresses.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Document the bindings for fsl,anatop-regulator
Signed-off-by: NYing-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: NSean Anderson <sean.anderson@seco.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

Anatop is an integrated regulator inside i.MX6 SoC.
There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
This patch adds the Anatop regulator driver.
Signed-off-by: NYing-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: NSean Anderson <sean.anderson@seco.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

Trying to compile with CONFIG_CMD_MMC=y and CONFIG_MMC=n leads to errors:

riscv64-linux-gnu-ld.bfd: cmd/built-in.o: in function `do_mmcops':
cmd/mmc.c:984: undefined reference to `get_mmc_num'
riscv64-linux-gnu-ld.bfd: cmd/built-in.o: in function `do_mmc_setdsr':
cmd/mmc.c:873: undefined reference to `find_mmc_device'

Add missing dependency.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

The fdt node offset is apparently not set properly when probed
causing no MDIO busses to be found. Fix this by obtaining the
offset.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
Reviewed-by: NStefan Roese <sr@denx.de>

After check for maximum between max id and available ports, also check
if available port count is less than max id and update.

In the case of the CN8030 OcteonTX SoC max_id needs to be reduced to
the number of ports found otherwise the following occurs on a scan:

GW6404-B> scsi scan
scanning bus for devices...
Target spinup took 0 ms.
AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
flags: 64bit ncq ilck stag pm led clo only pmp fbss pio slum part ccc
apst
  Device 0: (0:0) Vendor: ATA Prod.: SanDisk SD8SFAT0 Rev: Z233
            Type: Hard Disk
            Capacity: 61057.3 MB = 59.6 GB (125045424 x 512)
"Synchronous Abort" handler, esr 0x96000006
elr: 000000000052f824 lr : 000000000052fa10 (reloc)
elr: 000000007fee9824 lr : 000000007fee9a10
x0 : 0000000000000001 x1 : 0000000000000001
x2 : 000000007bea3528 x3 : 000000007bea3580
x4 : 0000000000000200 x5 : 0000000000000000
x6 : 0000000000000002 x7 : 000000007bea3540
x8 : 00000000fffffff8 x9 : 0000000000000008
x10: 00000000000186a0 x11: 000000000000000d
x12: 0000000000000006 x13: 000000000001869f
x14: 0000000000000007 x15: 00000000ffffffff
x16: 000000007ff439a5 x17: 000000007ff5730c
x18: 000000007bea9de0 x19: 000000007ff7a580
x20: 000000007bec79f8 x21: 0000000000000000
x22: 000000007bea3580 x23: 0000000000000000
x24: 0000000000000000 x25: 000000007bec7a00
x26: 00000000ffffffc0 x27: 000000007bec79d0
x28: 000000007beb51c0 x29: 000000007bea3480

Code: 91246800 940130c2 12800000 1400004f (b9402ae0)
Resetting CPU ...
Signed-off-by: NSuneel Garapati <sgarapati@marvell.com>
Reviewed-by: NStefan Roese <sr@denx.de>

Revert a change that occured between the Marvell SDK-10.1.1.0
and SDK-10.3.1.1 which broke QSMII phy support.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

The OcteonTX uses ARM's SBSA Watchdog device
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
Reviewed-by: NStefan Roese <sr@denx.de>

Support Generic Distro Default config
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
Reviewed-by: NStefan Roese <sr@denx.de>

Move CONFIG_SUPPORT_RAW_INITRD out of the octeontx_common header
and into the defconfig files.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
Reviewed-by: NStefan Roese <sr@denx.de>

Signed-off-by: NKarl Beldan <karl.beldan+oss@gmail.com>

Fixes IDE issues found on the Malta board under Qemu:

1) DMA implied commands were sent to the controller in stead of the PIO
variants. The rest of the code is DMA free and written for PIO operation.

2) direct pointer access was used to read and write the registers instead
of the inb/inw/outb/outw functions/macros. Registers don't have to be
memory mapped and ATA_CURR_BASE() does not have to return an offset from
address zero.

3) Endian isues in ide_ident() and reading/writing data in general. Names
were corrupted and sizes misreported.

Tested malta_defconfig and maltael_defconfig to work again in Qemu.
Signed-off-by: NReinoud Zandijk <reinoud@NetBSD.org>
Tested-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Enable IRQ using select for sandbox architecture.
Signed-off-by: NWasim Khan <wasim.khan@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

use 'select' to enable IRQ as it does not have architecture
specific dependency.
Signed-off-by: NWasim Khan <wasim.khan@nxp.com>
Reviewed-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

GIC_V3_ITS uses UCLASS_IRQ driver. Update Kconfig to select
IRQ when GIC_V3_ITS is enabled.
Signed-off-by: NWasim Khan <wasim.khan@nxp.com>
Reviewed-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Tested-by: NVladimir Oltean <vladimir.oltean@nxp.com>

UCLASS_IRQ driver is not Intel specific. Make CONFIG_IRQ
selectable for all platforms.
Signed-off-by: NWasim Khan <wasim.khan@nxp.com>
Tested-by: NVladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables
must contain only zeros on initial allocation, and this must be visible
to the Redistributors, or else the effect is UNPREDICTABLE".

And as the following statement, we here clear the whole Pending tables
instead of the first 1KB.
"An LPI Pending table that contains only zeros, including in the first 1KB,
indicates that there are no pending LPIs.
The first 1KB of the LPI Pending table is IMPLEMENTATION DEFINED. However,
if the first 1KB of the LPI Pending table and the rest of the table contain
only zeros, this must indicate that there are no pending LPIs."

And there isn't any pending LPI under U-Boot, so it's unnecessary to
load the contents of the Pending table during the enablement, then set
the GICR_PENDBASER.PTZ flag.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> # NXP LS1028A
Reviewed-by: NWasim Khan <wasim.khan@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Let's add a boot target for NVMe so we can do a full boot over NVMe.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Now we have PCIe, let's also enable NVMe to access an eventual NVMe SSDs
connected on the M.2 slot.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Enable PCIe by default in u-boot, this should eventually be made dynamic
in the runtime board config depending on the MCU configuration.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Add the PCIe part of the G12A USB3 PCIe Combo PHY driver.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Add missing gates used for PCIe.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

The sync of the device tree and dt-bindings from Linux v5.6-rc2
11a48a5a18c6 ("Linux 5.6-rc2") causes Ethernet to break on some
ODROID-C2. The PHY seems to need proper reset timing to be functional
in U-Boot and Linux afterwards. Readd the old PHY reset bindings for
dwmac until we support the new bindings in the PHY node.

Fixes: dd5f2351 ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Second set of u-boot-atmel features for 2021.07 cycle:

This small feature set include support for 5th PIO bank on pio4 pinctrl
driver and a fix for the SPL on sama5d3.

This reverts commit 38d6b7eb.

struct global_data contains a pointer to the bd_info structure. This
pointer was populated spl_set_bd() to a pre-allocated bd_info in the
".data" section. The referenced commit replaced this mechanism to one
that uses malloc(). That new mechanism is only used if SPL_ALLOC_BD=y.
which very few boards do.

The result is that (struct global_data)->bd is NULL in SPL on most
platforms. This breaks falcon mode, since arch_fixup_fdt() tries to
access (struct global_data)->bd and set the "/memory" node in the
devicetree. The result is that the "/memory" node contains garbage
values, causing linux to panic() as it sets up the page table.

Instead of trying to fix the mess, potentially causing other issues,
revert to the code that worked, while this change is reworked.
Signed-off-by: NAlexandru Gagniuc <mr.nuke.me@gmail.com>

in the early SPL boot stage whenever there is a call to udelay,
dm_timer_init fails to find the pit timer whenever it traverses
the device tree, if this property is not present
Signed-off-by: NManuel Reis <mluis.reis@gmail.com>
CC: Eugen Hristev <eugen.hristev@microchip.com>
Tested-by: NDerald D. Woods <woods.technical@gmail.com>
Reviewed-by: NEugen Hristev <eugen.hristev@microchip.com>

Change the pinctrl compatible to sama7g5, the right one for this product.
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>

Add support for sama7g5 pinctrl variant, with 5 banks with a degraded
8 line only 5th bank.
Based on Linux Kernel implementation.
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>

Pull request for efi-2021-07-rc1-2

Documentation:
	man-page for fatinfo

Bug fixes:
	memory leak in efi_capsule_scan_dir()
	incorrect invocations of EFI_CALL macro creating ESRT table
	buffer overflow in tcg2_create_digest()

This is a patchset which makes away with the .bind() controller indexing
workaround which was broken since before v2021.04, and then adds PHY
support and MX8M support on top of that. Better add it into the release
early to get as much testing as possible done, because this really does
a lot of changes to the ehci-mx6 driver.

- Support for pinmux status command on beaglebone
- Updates for MMC speed modes for J721e-evm
- Fix MMC booting on omap35_logic_somlv board

- SPI Flash ENV improvements / cleanups
- Redundant support for FAT
- Assorted bugfixes

Enable USB host support on MX8MM Verdin.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Max Krummenacher <max.krummenacher@toradex.com>
Cc: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>

The iMX8M uses nop PHY, select PHY and NOP_PHY automatically.
Otherwise, the DM capable driver is now perfectly compatible.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>

Fix cast from pointer to integer of different size by casting the
pointer to uintptr_t instead of uint32_t, the former has correct
size on both 32bit and 64bit architectures.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>

Add new compatible string, used by some more up-to-date DTs.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>

There is now multiple copies of CONFIG_MXC_USB_PORTSC in configs set to
PORT_PTS_UTMI | PORT_PTS_PTW, which is in fact the default register value
for MX6, MX7 and MX7ULP. Define the default value of CONFIG_MXC_USB_PORTSC
in the driver and use it in case CONFIG_MXC_USB_PORTSC is not defined in
config, to reduce the duplication.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>