The Parrot Board is an evaluation board with an Allwinner R16 (assumed
to be close to an Allwinner A33), 4GB of eMMC, 512MB of RAM, USB host
and OTG, a WiFi/Bluetooth combo chip, a micro SD Card reader, 2
controllable buttons, an LVDS port with separated backlight and
capacitive touch panel ports, an audio/microphone jack, a camera CSI
port, 2 sets of 22 GPIOs and an accelerometer.

The DTS file is identical to the one submitted to the upstream kernel.
Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

Commit b19236fd ("sunxi: Increase SPL header size to 64 bytes to avoid
code corruption") Added defines for MMC0 and SPI as boot identification.
After verifying on an OLinuXino Lime2 with NAND and eMMC, the expected
values have been confirmed and added to spl.h
Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

The switch to simple_printf was causing the SPL dram info to show as:

DRAM: u MiB

This fixes this by switching from %lu to %d for printing the DRAM size.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Signed-off-by: NTom Rini <trini@konsulko.com>

Otherwise,  ocassionally see errors like this:
  Flashing sparse image at offset 2078720
  Flashing Sparse Image
  sdhci_send_command: Timeout for status update!
  mmc fail to send stop cmd
  write_sparse_image: Write failed, block #2181088 [0]

This does not affect the actual writing speed, which is controlled by
the default value:
  CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT

It only increases the retries when reading:
  SDHCI_INT_STATUS
to avoid the timeout error.
Signed-off-by: NSteve Rae <steve.rae@raedomain.com>
Reviewed-by: NStefan Roese <sr@denx.de>
Tested-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: NJaehoon Chung <jh80.chung@samsung.com>

DRA72-Evm revC uses dra72-evm-revc.dtb. Update the same in env vatiables.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Move the bootdelay >= 0 check to the caller, which simplifies
the callees.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NStefan Roese <sr@denx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Factor out the same code from the callees to the caller.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NStefan Roese <sr@denx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Because abortboot_keyed() and abortboot_normal() are not compiled
at the same time, we can rename both of them to __abortboot().
This allows to drop #ifdef from the caller.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NStefan Roese <sr@denx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NHeiko Schocher <hs@denx.de>

As the help message of CONFIG_BOOTDELAY says, CONFIG_BOOTDELAY=-2
means the autoboot with no delay, with no abort check even if
CONFIG_ZERO_BOOTDELAY_CHECK is defined.

To sum up, the autoboot behaves as follows:

 [1] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=y
    autoboot with no delay, but you can abort it by key input

 [2] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n
    autoboot with no delay, with no check for abort

 [3] CONFIG_BOOTDELAY=-1
    disable autoboot

 [4] CONFIG_BOOTDELAY=-2
    autoboot with no delay, with no check for abort

As you notice, [2] and [4] come to the same result, which means we
do not need CONFIG_ZERO_BOOTDELAY_CHECK.  We can control all the
cases only by CONFIG_BOOTDELAY, like this:

 [1] CONFIG_BOOTDELAY=0
    autoboot with no delay, but you can abort it by key input

 [2] CONFIG_BOOTDELAY=-1
    disable autoboot

 [3] CONFIG_BOOTDELAY=-2
    autoboot with no delay, with no check for abort

This commit converts the logic as follow:
  CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n
    --> CONFIG_BOOTDELAY=-2
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NStefan Roese <sr@denx.de>
Acked-by: NIgor Grinberg <grinberg@compulab.co.il>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Acked-by: NVladimir Zapolskiy <vz@mleia.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>
Acked-by: NChristian Riesch <christian.riesch@omicronenergy.com>
Acked-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com>

The same information now exists in common/Kconfig.  Do not duplicate
documentation from the point of view of maintainability.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NHeiko Schocher <hs@denx.de>

This recently added board missed the tree-wide migration of
CONFIG_BOOTDELAY.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NPavel Machek <pavel@denx.de>
Reviewed-by: NHeiko Schocher <hs@denx.de>
Reviewed-by: NStefan Roese <sr@denx.de>

Align the name of the defconfig file for high-security (HS) device variants
from the AM43xx family of SoCs with the corresponding name used for the
general purpose devices. This allows for easier cross-association of those
files and also provides room to grow from an HS device part number
perspective.

Furthermore, update and cleanup associated MAINTAINERS file.
Signed-off-by: NAndreas Dannenberg <dannenberg@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Madan Srinivas <madans@ti.com>

Correcting QSPI disable/unselect CS reset value.
CTRL_CORE_CONTROL_IO_2: QSPI_MEMMAPPED_CS[10:8]

This is not causing any issue, but its better
to untouch the reserved bits.

Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: NRavi Babu <ravibabu@ti.com>

I will carry this work-around until it is cared in the kernel.
This looks up the AIDET node and sets up a register to handle
active low interrupt signals.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The AIDET (ARM Interrupt Detector Add-on Circuit) is a kind of
syscon block related with the interrupt controller.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

SPL does not use all of the devices, so we can save some memory
footprint.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration
(pin biasing, drive strength control), but not pin-muxing.

Allow to fill the mux value table with -1 for those pins; pins with
mux value -1 will be skipped in the pin-mux set function.  The mux
value type should be changed from "unsigned" to "int" in order to
accommodate -1 as a special case.

[ Linux commit: 363c90e743b50a432a91a211dd8b078d9df446e9 ]
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

PH1-LD11 and PH1-LD20 have much pin controlling in common, so I
added a single driver shared between them in the initial commit.

However, the Ethernet pin-mux settings I am going to add are
different with each other, and they may diverge more as the
progress of development.  Split it into two dedicated drivers.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Currently, the UniPhier pinctrl driver itself is a syscon, but it
turned out much more reasonable to make it a child node of a syscon
because our syscon node consists of a bunch of system configuration
registers, not only pinctrl, but also phy, and misc registers.
It is difficult to split the node.  This commit allows to migrate to
the new DT structure.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

I periodically sync Device Trees for better maintainability.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This SoC does not support NAND CS1.  This place-holder is no longer
necessary.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

My mistake in the initial support patch.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These are pin group names, not function names.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

There is a dummy pch driver in the coreboot directory. This causes
drivers of its children fail to function due to empty ops. Remove
the whole file since it is no longer needed.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NTom Rini <trini@konsulko.com>

Currently layescape SoCs are not using cpu nodes. So removing
them in favour of compatibly with  similar SoCs that
have different cores like LS2080A and LS2088A.

This has been tested on LS2080AQDS, LS1043ARDB, LS1012ARDB.
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: NAbhimanyu Saini <abhimanyu.saini@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs.
like LS2080A, LS1043A, LS1012A.

So append "A" to SoC names.
Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.

Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.

If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN,
HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec
register. The driver uses RSTA to replace the clock gate off
operation. But this is not a good solution because:
1. when using RSTA, we should wait this bit to clear by itself. This is not
   implemeneted in the code.
2. After RSTA is set, it is recommended that the Host Driver reset the
   external card and reinitialize it.

So in this patch, we change to use the vendorspec registers for these bits
operation.
Signed-off-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

When booting in eMMC fast boot, MMC host does not exit from
boot mode after bootrom loading image. So the first command
'CMD0' sent in uboot will pull down the CMD line to low and
cause errors.

This patch cleans the MMC boot register in "mmc_init" to put the
MMC host back to normal mode.

Also clear DLL_CTRL delay line settings at USDHC initialization
to eliminate the pre-settings from boot rom.
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Now I2C is initialized early enough to access FPGA so it supports to
show board info as early as other boot methods.
Signed-off-by: NGong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Get the clocks from FPGA through I2C, if IFC is disabled.
Signed-off-by: NGong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Add CONFIG_{SD|NAND|ONENAND|SPI|QSPI|SATA}_BOOT kconfig entries.

SoCs supports loading U-Boot from different medias to DRAM, such as
i.MX6/7 supports loading U-Boot to DRAM from sd/emmc/nand/qspi/spi/sata
and etc. For i.MX, imximage will generate different IVT headers according
to boot medias.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Francois Retief <fgretief@spaceteq.co.za>
Cc: Tom Rini <trini@konsulko.com>

Not only am335x supports booting from NOR, i.MX6 SoCs also
supports booting from NOR. Make NOR_BOOT a common
option to let different SoCs share it.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Francois Retief <fgretief@spaceteq.co.za>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Update the email address for the boards that I maintain.
Signed-off-by: NSteve Rae <steve.rae@raedomain.com>