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44faff24
编写于
6月 28, 2016
作者:
T
Tom Rini
浏览文件
操作
浏览文件
下载
差异文件
Merge
git://git.denx.de/u-boot-fsl-qoriq
上级
6f0aea39
dee01e42
变更
12
隐藏空白更改
内联
并排
Showing
12 changed file
with
94 addition
and
151 deletion
+94
-151
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+5
-3
arch/arm/cpu/armv8/fsl-layerscape/soc.c
arch/arm/cpu/armv8/fsl-layerscape/soc.c
+2
-2
arch/arm/dts/fsl-ls1012a.dtsi
arch/arm/dts/fsl-ls1012a.dtsi
+0
-12
arch/arm/dts/fsl-ls1043a.dtsi
arch/arm/dts/fsl-ls1043a.dtsi
+0
-32
arch/arm/dts/fsl-ls2080a.dtsi
arch/arm/dts/fsl-ls2080a.dtsi
+0
-61
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+7
-7
arch/arm/include/asm/arch-fsl-layerscape/soc.h
arch/arm/include/asm/arch-fsl-layerscape/soc.h
+7
-7
board/freescale/ls1043aqds/ls1043aqds.c
board/freescale/ls1043aqds/ls1043aqds.c
+7
-5
drivers/mmc/fsl_esdhc.c
drivers/mmc/fsl_esdhc.c
+54
-14
drivers/usb/common/fsl-errata.c
drivers/usb/common/fsl-errata.c
+2
-2
include/configs/ls1043aqds.h
include/configs/ls1043aqds.h
+3
-6
include/fsl_esdhc.h
include/fsl_esdhc.h
+7
-0
未找到文件。
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
浏览文件 @
44faff24
...
...
@@ -11,6 +11,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/soc.h>
#include <fsl_ifc.h>
#include "cpu.h"
DECLARE_GLOBAL_DATA_PTR
;
...
...
@@ -47,7 +48,7 @@ void get_sys_info(struct sys_info *sys_info)
[
5
]
=
2
,
/* CC2 PPL / 2 */
};
uint
i
;
uint
i
,
cluster
;
uint
freq_c_pll
[
CONFIG_SYS_FSL_NUM_CC_PLLS
];
uint
ratio
[
CONFIG_SYS_FSL_NUM_CC_PLLS
];
unsigned
long
sysclk
=
CONFIG_SYS_CLK_FREQ
;
...
...
@@ -80,8 +81,9 @@ void get_sys_info(struct sys_info *sys_info)
freq_c_pll
[
i
]
=
sys_info
->
freq_systembus
*
ratio
[
i
];
}
for
(
cpu
=
0
;
cpu
<
CONFIG_MAX_CPUS
;
cpu
++
)
{
u32
c_pll_sel
=
(
in_be32
(
&
clk
->
clkcsr
[
cpu
].
clkcncsr
)
>>
27
)
for_each_cpu
(
i
,
cpu
,
cpu_numcores
(),
cpu_mask
())
{
cluster
=
fsl_qoriq_core_to_cluster
(
cpu
);
u32
c_pll_sel
=
(
in_be32
(
&
clk
->
clkcsr
[
cluster
].
clkcncsr
)
>>
27
)
&
0xf
;
u32
cplx_pll
=
core_cplx_pll
[
c_pll_sel
];
...
...
arch/arm/cpu/armv8/fsl-layerscape/soc.c
浏览文件 @
44faff24
...
...
@@ -28,7 +28,7 @@ bool soc_has_dp_ddr(void)
u32
svr
=
gur_in32
(
&
gur
->
svr
);
/* LS2085A has DP_DDR */
if
(
SVR_SOC_VER
(
svr
)
==
SVR_LS2085
)
if
(
SVR_SOC_VER
(
svr
)
==
SVR_LS2085
A
)
return
true
;
return
false
;
...
...
@@ -40,7 +40,7 @@ bool soc_has_aiop(void)
u32
svr
=
gur_in32
(
&
gur
->
svr
);
/* LS2085A has AIOP */
if
(
SVR_SOC_VER
(
svr
)
==
SVR_LS2085
)
if
(
SVR_SOC_VER
(
svr
)
==
SVR_LS2085
A
)
return
true
;
return
false
;
...
...
arch/arm/dts/fsl-ls1012a.dtsi
浏览文件 @
44faff24
...
...
@@ -9,18 +9,6 @@
/ {
compatible = "fsl,ls1012a";
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
clocks = <&clockgen 1 0>;
};
};
sysclk: sysclk {
compatible = "fixed-clock";
...
...
arch/arm/dts/fsl-ls1043a.dtsi
浏览文件 @
44faff24
...
...
@@ -15,38 +15,6 @@
/ {
compatible = "fsl,ls1043a";
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
clocks = <&clockgen 1 0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
clocks = <&clockgen 1 0>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
clocks = <&clockgen 1 0>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
clocks = <&clockgen 1 0>;
};
};
sysclk: sysclk {
compatible = "fixed-clock";
...
...
arch/arm/dts/fsl-ls2080a.dtsi
浏览文件 @
44faff24
...
...
@@ -12,67 +12,6 @@
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
/*
* We expect the enable-method for cpu's to be "psci", but this
* is dependent on the SoC FW, which will fill this in.
*
* Currently supported enable-method is psci v0.2
*/
/* We have 4 clusters having 2 Cortex-A57 cores each */
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
};
cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x200>;
};
cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x201>;
};
cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x300>;
};
cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x301>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>;
...
...
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
浏览文件 @
44faff24
...
...
@@ -8,13 +8,13 @@
#define _FSL_LAYERSCAPE_CPU_H
static
struct
cpu_type
cpu_type_list
[]
=
{
CPU_TYPE_ENTRY
(
LS2080
,
LS2080
,
8
),
CPU_TYPE_ENTRY
(
LS2085
,
LS2085
,
8
),
CPU_TYPE_ENTRY
(
LS2045
,
LS2045
,
4
),
CPU_TYPE_ENTRY
(
LS1043
,
LS1043
,
4
),
CPU_TYPE_ENTRY
(
LS1023
,
LS1023
,
2
),
CPU_TYPE_ENTRY
(
LS2040
,
LS2040
,
4
),
CPU_TYPE_ENTRY
(
LS1012
,
LS1012
,
1
),
CPU_TYPE_ENTRY
(
LS2080
A
,
LS2080A
,
8
),
CPU_TYPE_ENTRY
(
LS2085
A
,
LS2085A
,
8
),
CPU_TYPE_ENTRY
(
LS2045
A
,
LS2045A
,
4
),
CPU_TYPE_ENTRY
(
LS1043
A
,
LS1043A
,
4
),
CPU_TYPE_ENTRY
(
LS1023
A
,
LS1023A
,
2
),
CPU_TYPE_ENTRY
(
LS2040
A
,
LS2040A
,
4
),
CPU_TYPE_ENTRY
(
LS1012
A
,
LS1012A
,
1
),
};
#ifndef CONFIG_SYS_DCACHE_OFF
...
...
arch/arm/include/asm/arch-fsl-layerscape/soc.h
浏览文件 @
44faff24
...
...
@@ -41,13 +41,13 @@ struct cpu_type {
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
#define SVR_WO_E 0xFFFFFE
#define SVR_LS1012 0x870400
#define SVR_LS1043 0x879200
#define SVR_LS1023 0x879208
#define SVR_LS2045 0x870120
#define SVR_LS2080 0x870110
#define SVR_LS2085 0x870100
#define SVR_LS2040 0x870130
#define SVR_LS1012
A
0x870400
#define SVR_LS1043
A
0x879200
#define SVR_LS1023
A
0x879208
#define SVR_LS2045
A
0x870120
#define SVR_LS2080
A
0x870110
#define SVR_LS2085
A
0x870100
#define SVR_LS2040
A
0x870130
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
...
...
board/freescale/ls1043aqds/ls1043aqds.c
浏览文件 @
44faff24
...
...
@@ -47,7 +47,7 @@ enum {
int
checkboard
(
void
)
{
char
buf
[
64
];
#if
!defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
#if
ndef CONFIG_SD_BOOT
u8
sw
;
#endif
...
...
@@ -55,8 +55,6 @@ int checkboard(void)
#ifdef CONFIG_SD_BOOT
puts
(
"SD
\n
"
);
#elif defined(CONFIG_QSPI_BOOT)
puts
(
"QSPI
\n
"
);
#else
sw
=
QIXIS_READ
(
brdcfg
[
0
]);
sw
=
(
sw
&
QIXIS_LBMAP_MASK
)
>>
QIXIS_LBMAP_SHIFT
;
...
...
@@ -67,8 +65,8 @@ int checkboard(void)
puts
(
"PromJet
\n
"
);
else
if
(
sw
==
0x9
)
puts
(
"NAND
\n
"
);
else
if
(
sw
==
0x
15
)
printf
(
"
IFCCard
\n
"
);
else
if
(
sw
==
0x
F
)
printf
(
"
QSPI
\n
"
);
else
printf
(
"invalid setting of SW%u
\n
"
,
QIXIS_LBMAP_SWITCH
);
#endif
...
...
@@ -232,6 +230,10 @@ int board_early_init_f(void)
#ifdef CONFIG_LPUART
u8
uart
;
#endif
#ifdef CONFIG_SYS_I2C_EARLY_INIT
i2c_early_init_f
();
#endif
fsl_lsch2_early_init_f
();
#ifdef CONFIG_HAS_FSL_XHCI_USB
...
...
drivers/mmc/fsl_esdhc.c
浏览文件 @
44faff24
...
...
@@ -56,21 +56,27 @@ struct fsl_esdhc {
uint
fevt
;
/* Force event register */
uint
admaes
;
/* ADMA error status register */
uint
adsaddr
;
/* ADMA system address register */
char
reserved2
[
100
];
/* reserved */
uint
vendorspec
;
/* Vendor Specific register */
char
reserved3
[
56
];
/* reserved */
char
reserved2
[
4
];
uint
dllctrl
;
uint
dllstat
;
uint
clktunectrlstatus
;
char
reserved3
[
84
];
uint
vendorspec
;
uint
mmcboot
;
uint
vendorspec2
;
char
reserved4
[
48
];
uint
hostver
;
/* Host controller version register */
char
reserved4
[
4
];
/* reserved */
uint
dmaerraddr
;
/* DMA error address register */
char
reserved5
[
4
];
/* reserved */
uint
dmaerra
ttr
;
/* DMA error attribute
register */
uint
dmaerra
ddr
;
/* DMA error address
register */
char
reserved6
[
4
];
/* reserved */
uint
dmaerrattr
;
/* DMA error attribute register */
char
reserved7
[
4
];
/* reserved */
uint
hostcapblt2
;
/* Host controller capabilities register 2 */
char
reserved
7
[
8
];
/* reserved */
char
reserved
8
[
8
];
/* reserved */
uint
tcr
;
/* Tuning control register */
char
reserved
8
[
28
];
/* reserved */
char
reserved
9
[
28
];
/* reserved */
uint
sddirctl
;
/* SD direction control register */
char
reserved
9
[
712
];
/* reserved */
char
reserved
10
[
712
];
/* reserved */
uint
scr
;
/* eSDHC control register */
};
...
...
@@ -85,7 +91,9 @@ struct fsl_esdhc {
* Following is used when Driver Model is enabled for MMC
* @dev: pointer for the device
* @non_removable: 0: removable; 1: non-removable
* @wp_enable: 1: enable checking wp; 0: no check
* @cd_gpio: gpio for card detection
* @wp_gpio: gpio for write protection
*/
struct
fsl_esdhc_priv
{
struct
fsl_esdhc
*
esdhc_regs
;
...
...
@@ -95,7 +103,9 @@ struct fsl_esdhc_priv {
struct
mmc
*
mmc
;
struct
udevice
*
dev
;
int
non_removable
;
int
wp_enable
;
struct
gpio_desc
cd_gpio
;
struct
gpio_desc
wp_gpio
;
};
/* Return the XFERTYP flags for a given command and data packet */
...
...
@@ -239,9 +249,12 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
#endif
if
(
wml_value
>
WML_WR_WML_MAX
)
wml_value
=
WML_WR_WML_MAX_VAL
;
if
((
esdhc_read32
(
&
regs
->
prsstat
)
&
PRSSTAT_WPSPL
)
==
0
)
{
printf
(
"
\n
The SD card is locked. Can not write to a locked card.
\n\n
"
);
return
TIMEOUT
;
if
(
priv
->
wp_enable
)
{
if
((
esdhc_read32
(
&
regs
->
prsstat
)
&
PRSSTAT_WPSPL
)
==
0
)
{
printf
(
"
\n
The SD card is locked. Can not write to a locked card.
\n\n
"
);
return
TIMEOUT
;
}
}
esdhc_clrsetbits32
(
&
regs
->
wml
,
WML_WR_WML_MASK
,
...
...
@@ -532,7 +545,7 @@ static void set_sysctl(struct mmc *mmc, uint clock)
clk
=
(
pre_div
<<
8
)
|
(
div
<<
4
);
#ifdef CONFIG_FSL_USDHC
esdhc_
setbits32
(
&
regs
->
sysctl
,
SYSCTL_RSTA
);
esdhc_
clrbits32
(
&
regs
->
vendorspec
,
VENDORSPEC_CKEN
);
#else
esdhc_clrbits32
(
&
regs
->
sysctl
,
SYSCTL_CKEN
);
#endif
...
...
@@ -542,7 +555,7 @@ static void set_sysctl(struct mmc *mmc, uint clock)
udelay
(
10000
);
#ifdef CONFIG_FSL_USDHC
esdhc_
clrbits32
(
&
regs
->
sysctl
,
SYSCTL_RSTA
);
esdhc_
setbits32
(
&
regs
->
vendorspec
,
VENDORSPEC_PEREN
|
VENDORSPEC_CKEN
);
#else
esdhc_setbits32
(
&
regs
->
sysctl
,
SYSCTL_PEREN
|
SYSCTL_CKEN
);
#endif
...
...
@@ -616,6 +629,20 @@ static int esdhc_init(struct mmc *mmc)
while
((
esdhc_read32
(
&
regs
->
sysctl
)
&
SYSCTL_RSTA
)
&&
--
timeout
)
udelay
(
1000
);
#if defined(CONFIG_FSL_USDHC)
/* RSTA doesn't reset MMC_BOOT register, so manually reset it */
esdhc_write32
(
&
regs
->
mmcboot
,
0x0
);
/* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
esdhc_write32
(
&
regs
->
mixctrl
,
0x0
);
esdhc_write32
(
&
regs
->
clktunectrlstatus
,
0x0
);
/* Put VEND_SPEC to default value */
esdhc_write32
(
&
regs
->
vendorspec
,
VENDORSPEC_INIT
);
/* Disable DLL_CTRL delay line */
esdhc_write32
(
&
regs
->
dllctrl
,
0x0
);
#endif
#ifndef ARCH_MXC
/* Enable cache snooping */
esdhc_write32
(
&
regs
->
scr
,
0x00000040
);
...
...
@@ -623,6 +650,8 @@ static int esdhc_init(struct mmc *mmc)
#ifndef CONFIG_FSL_USDHC
esdhc_setbits32
(
&
regs
->
sysctl
,
SYSCTL_HCKEN
|
SYSCTL_IPGEN
);
#else
esdhc_setbits32
(
&
regs
->
vendorspec
,
VENDORSPEC_HCKEN
|
VENDORSPEC_IPGEN
);
#endif
/* Set the initial clock speed */
...
...
@@ -699,6 +728,7 @@ static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
priv
->
esdhc_regs
=
(
struct
fsl_esdhc
*
)(
unsigned
long
)(
cfg
->
esdhc_base
);
priv
->
bus_width
=
cfg
->
max_bus_width
;
priv
->
sdhc_clk
=
cfg
->
sdhc_clk
;
priv
->
wp_enable
=
cfg
->
wp_enable
;
return
0
;
};
...
...
@@ -720,6 +750,9 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
#ifndef CONFIG_FSL_USDHC
esdhc_setbits32
(
&
regs
->
sysctl
,
SYSCTL_PEREN
|
SYSCTL_HCKEN
|
SYSCTL_IPGEN
|
SYSCTL_CKEN
);
#else
esdhc_setbits32
(
&
regs
->
vendorspec
,
VENDORSPEC_PEREN
|
VENDORSPEC_HCKEN
|
VENDORSPEC_IPGEN
|
VENDORSPEC_CKEN
);
#endif
writel
(
SDHCI_IRQ_EN_BITS
,
&
regs
->
irqstaten
);
...
...
@@ -938,6 +971,13 @@ static int fsl_esdhc_probe(struct udevice *dev)
&
priv
->
cd_gpio
,
GPIOD_IS_IN
);
}
priv
->
wp_enable
=
1
;
ret
=
gpio_request_by_name_nodev
(
fdt
,
node
,
"wp-gpios"
,
0
,
&
priv
->
wp_gpio
,
GPIOD_IS_IN
);
if
(
ret
)
priv
->
wp_enable
=
0
;
/*
* TODO:
* Because lack of clk driver, if SDHC clk is not enabled,
...
...
drivers/usb/common/fsl-errata.c
浏览文件 @
44faff24
...
...
@@ -182,8 +182,8 @@ bool has_erratum_a008751(void)
switch
(
soc
)
{
#ifdef CONFIG_ARM64
case
SVR_LS2080
:
case
SVR_LS2085
:
case
SVR_LS2080
A
:
case
SVR_LS2085
A
:
return
IS_SVR_REV
(
svr
,
1
,
0
);
#endif
}
...
...
include/configs/ls1043aqds.h
浏览文件 @
44faff24
...
...
@@ -10,11 +10,7 @@
#include "ls1043a_common.h"
#define CONFIG_DISPLAY_CPUINFO
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_DISPLAY_BOARDINFO_LATE
#else
#define CONFIG_DISPLAY_BOARDINFO
#endif
#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_TEXT_BASE 0x82000000
...
...
@@ -29,8 +25,8 @@ unsigned long get_board_sys_clk(void);
unsigned
long
get_board_ddr_clk
(
void
);
#endif
#define CONFIG_SYS_CLK_FREQ
100000000
#define CONFIG_DDR_CLK_FREQ
100000000
#define CONFIG_SYS_CLK_FREQ
get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ
get_board_ddr_clk()
#define CONFIG_SKIP_LOWLEVEL_INIT
...
...
@@ -225,6 +221,7 @@ unsigned long get_board_ddr_clk(void);
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_QIXIS_I2C_ACCESS
#define CONFIG_SYS_I2C_EARLY_INIT
#define CONFIG_SYS_NO_FLASH
#endif
...
...
include/fsl_esdhc.h
浏览文件 @
44faff24
...
...
@@ -35,6 +35,12 @@
#define SYSCTL_RSTC 0x02000000
#define SYSCTL_RSTD 0x04000000
#define VENDORSPEC_CKEN 0x00004000
#define VENDORSPEC_PEREN 0x00002000
#define VENDORSPEC_HCKEN 0x00001000
#define VENDORSPEC_IPGEN 0x00000800
#define VENDORSPEC_INIT 0x20007809
#define IRQSTAT 0x0002e030
#define IRQSTAT_DMAE (0x10000000)
#define IRQSTAT_AC12E (0x01000000)
...
...
@@ -171,6 +177,7 @@ struct fsl_esdhc_cfg {
phys_addr_t
esdhc_base
;
u32
sdhc_clk
;
u8
max_bus_width
;
u8
wp_enable
;
struct
mmc_config
cfg
;
};
...
...
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