Following next kernel rcc bindings, we must use a MFD
RCC driver which is able to bind both clock and reset
drivers.

We can reuse and adapt RCC MFD driver already available
for MCU SoCs (F4/F7/H7).
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Add support of fuse command (read/write/program/sense)
on bank 0 to access to BSEC SAFMEM (4096 OTP bits).
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Add a driver for RXAUI control on IHS FPGAs.
Signed-off-by: NMario Six <mario.six@gdsys.cc>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This patch added Kconfig support for CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET
and enabled it in respective defconfig.
Signed-off-by: NVipul Kumar <vipulk@xilinx.com>
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This patch adds the support of reset and clock control
block (rcc) found on STM32 SoCs.
This driver is similar to a MFD linux driver.

This driver supports currently STM32H7 only.
STM32F4 and STM32F7 will be migrated to this rcc MFD driver
in the future to uniformize all STM32 SoCs already upstreamed.
Signed-off-by: NChristophe Kerello <christophe.kerello@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NVikas Manocha <vikas.manocha@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This option is an SPL-variant of the I2C_EEPROM option to enable
the driver for generic I2C-attached EEPROMs for SPL.
Signed-off-by: NWenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add the following options to drivers/misc/Kconfig:
	SYS_I2C_EEPROM_ADDR
	SYS_I2C_EEPROM_BUS
	SYS_EEPROM_SIZE
	SYS_EEPROM_PAGE_WRITE_BITS
	SYS_EEPROM_PAGE_WRITE_DELAY_MS
	SYS_I2C_EEPROM_ADDR_LEN
	SYS_I2C_EEPROM_ADDR_OVERFLOW

This does not migrate any boards, but provides a foundations for
those who want/need these options
Signed-off-by: NAdam Ford <aford173@gmail.com>
[trini: Migrate uniphier]
Signed-off-by: NTom Rini <trini@konsulko.com>

This module can be found on the Turris Omnia board connected
via the I2C interface.

Among some cryptographic functions, the chip has a 512 bit
One Time Programmable memory, 88 byte configuration memory
and 512 byte general purpose memory.

The Turris Omnia stores serial number and device MAC address in
the OTP memory.

This commit adds basic support for reading the EEPROM and also
exposes the chips Random Number Generator.

The driver is based on code by
  Josh Datko, Cryptotronix, jbd@cryptotronix.com
and also
  Tomas Hlavacek, CZ.NIC, tomas.hlavacek@nic.cz
Signed-off-by: NTomas Hlavacek <tomas.hlavacek@nic.cz>
Signed-off-by: NMarek Behun <marek.behun@nic.cz>

 create mode 100644 drivers/misc/atsha204a-i2c.c
 create mode 100644 include/atsha204a-i2c.h
Signed-off-by: NStefan Roese <sr@denx.de>

This adds a simple driver for reading the efuse block of the RK3399.
It should be easy enough to add drivers for other devices (e.g. the
RK3328, RK3368, etc.) by passing the device details via driver_data.

Unlike the kernel driver (using the nvmem subsystem), we don't expose
the efuse as multiple named cells, but rather as a linear memory that
can be read using misc_read(...).

The primary use case (as of today) is the generation of a 'serial#'
(and a 'cpuid#') environment variable for the RK3399-Q7 (Puma)
system-on-module.

Note that this adds a debug-only (i.e. only if DEBUG is defined)
command 'rk3399_dump_efuses' that dumps the efuse block's content.
N.B.: The name 'rk3399_dump_efuses' was intentionally chosen to
      include a SoC-name (together with a comment in the function) to
      remind whoever adds support for additional SoCs that this
      function currently makes assumptions regarding the size of the
      fuse-box based on the RK3399. The hope is that the function is
      adjusted to reflect any changes resulting from generalising the
      driver for multiple SoCs and is then renamed.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This converts the following to Kconfig:
   CONFIG_DS4510
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

The Tegra CAR (Clock And Reset) module provides control of most clocks
and reset signals within the Tegra SoC. This change implements a driver
for this module. However, since the module implements multiple kinds of
services (clocks, resets, perhaps more), all this driver does is bind
various sub-devices, which in turn provide the real services. This driver
is essentially an "MFD" (Multi-Function Device) in Linux kernel speak.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

This simple driver provides some functions to control some of the
integrated devices. The watchdog is enabled per default. This driver
adds a function to disable the watchdog. Also the internal legacy
UART (io address 0x3f8/0x2f8) is enabled per default.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>

The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such as clocks, resets, power domains, PMIC I2C
bus, etc. This driver provides the core low-level communication path by
which feature-specific drivers (such as clock) can make requests to the
BPMP. This driver is similar to an MFD driver in the Linux kernel. It is
unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186
build of U-Boot will need the feature.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Create drivers/sysreset and move sysreset-uclass and all sysreset
drivers there.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

This patch implements the reading functionality for the generic I2C
EEPROM driver, which was just a non-functional stub until now.

Since the page size will be of importance for the writing support, we
add suitable members to the private data structure to keep track of it.

Compatibility strings for a range of at24c* chips are added.
Signed-off-by: NMario Six <mario.six@gdsys.cc>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NHeiko Schocher <hs@denx.de>

The current reset API implements a method to reset the entire system.
In the near future, I'd like to introduce code that implements the device
tree reset bindings; i.e. the equivalent of the Linux kernel's reset API.
This controls resets to individual HW blocks or external chips with reset
signals. It doesn't make sense to merge the two APIs into one since they
have different semantic purposes. Resolve the naming conflict by renaming
the existing reset API to sysreset instead, so the new reset API can be
called just reset.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW
Signed-off-by: NMiao Yan <yanmiaobest@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This patch splits qfw command interface and qfw core function into two
files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core.

Now when qfw command interface is enabled, it will automatically select
qfw core. This patch also makes the ACPI table generation select
CONFIG_QFW.
Signed-off-by: NMiao Yan <yanmiaobest@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Some devices need special sequences to be used when starting up. Add a
uclass for this. Drivers can be added to provide specific features as
needed.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add MXC_OCOTP Kconfig entry.
Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>

Convert altera sysid to driver model with misc uclass.
Signed-off-by: NThomas Chou <thomas@wytron.com.tw>
Acked-by: NChin Liang See <clsee@altera.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Implement a Miscellaneous uclass with generic read or
write operations. This class is used only for those
do not fit other more general classes.
Signed-off-by: NThomas Chou <thomas@wytron.com.tw>
Acked-by: NSimon Glass <sjg@chromium.org>

Should use FSL_SEC_MON, not CONFIG_FSL_SEC_MON as Kconfig entry.
Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Acked-by: NSimon Glass <sjg@chromium.org>

The menuconfig for drivers are getting more and more cluttered
and unreadable because too many entries are displayed in a single
flat menu.  Use hierarchic menu for each category.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
[trini: Update to apply again in a few places, drop USB hunk]
Signed-off-by: NTom Rini <trini@konsulko.com>

It is common for system reset to be available at multiple levels in modern
hardware. For example, an SoC may provide a reset option, and a board may
provide its own reset for reasons of security or thoroughness. It is useful
to be able to model this hardware without hard-coding the behaviour in the
SoC or board. Also there is a distinction sometimes between resetting just
the CPU (leaving GPIO state alone) and resetting all the PMICs, just cutting
power.

To achieve this, add a simple system reset uclass. It allows multiple devices
to provide reset functionality and provides a way to walk through them,
requesting a particular reset type until is it provided.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This patch adds a driver for the PCA9551 LED controller.
Originated-by: NTimo Herbrecher <t.herbrecher@gateware.de>
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NTom Rini <trini@konsulko.com>
Cc: Fabio Estevam <festevam@gmail.com>
Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com>

Move CONFIG_CROS_EC_SANDBOX to Kconfig.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Since all supported boards enable this option now, we can remove it along
with the old code.
Signed-off-by: NSimon Glass <sjg@chromium.org>

The Security Monitor is the SOC’s central reporting point for
security-relevant events such as the success or failure of boot
software validation and the detection of potential security compromises.

The API's for transition of Security states have been added
which will be used in case of SECURE BOOT.
Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: NGaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Since both I2C and SPI are converted to Kconfig, we can convert cros_ec
to Kconfig for these buses.

LPC will need to wait until driver mode PCI is available.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Expand the help messages for each driver. Add missing Kconfig for I2C,
SPI flash and thermal.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

This would be useful to start moving various config options.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>

This commit adds:
 - arch/${ARCH}/Kconfig
    provide a menu to select target boards
 - board/${VENDOR}/${BOARD}/Kconfig or board/${BOARD}/Kconfig
    set CONFIG macros to the appropriate values for each board
 - configs/${TARGET_BOARD}_defconfig
    default setting of each board

(This commit was automatically generated by a conversion script
based on boards.cfg)

In Linux Kernel, defconfig files are located under
arch/${ARCH}/configs/ directory.
It works in Linux Kernel since ARCH is always given from the
command line for cross compile.

But in U-Boot, ARCH is not given from the command line.
Which means we cannot know ARCH until the board configuration is done.
That is why all the "*_defconfig" files should be gathered into a
single directory ./configs/.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: NSimon Glass <sjg@chromium.org>