Set BM poll size once during priv probe and do not
overwrite it during port probe procedure. Pool is common for
all CP ports.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NNadav Haklai <nadavh@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

TX drain in transmit procedure could cause issues due
to race between drain procedure and transmition of descriptor
between AGGR TXQ and physical TXQ.
TXQ will be cleared before moving to Linux by stop procedure.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NNadav Haklai <nadavh@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

MVPP22 driver support 64 Bit arch and require BM pool
high address configuration.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NNadav Haklai <nadavh@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Remove IRQ configuration from U-Boot PP driver.
U-Boot don't use interrupts and configuration of IRQ in U-Boot
caused crashes in Linux shared interrupt mode.
Also interrupt use is redundant in RX routine since a single RX
queue is used.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NNadav Haklai <nadavh@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

MBUS driver were replaced by AXI in PPv22 and relevant
only for PPv21.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NNadav Haklai <nadavh@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

U-boot use single physical tx queue with size 16 descriptors.
So aggregated tx queue size should be equal to physical tx queue
and cpu descriptor chunk(number of descriptors delivered from
physical tx queue to aggregated tx queue by one chunk) shouldn't be
larger than physical tx queue.

Fix:
Set AGGR_TXQ and CPU_DESC_CHUNK to be 16 descriptors, same as
physical TXQ.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NNadav Haklai <nadavh@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Issue:
BM counters were overrun by probe that called per Network interface and
caused release of wrong number of buffers during remove procedure.

Fix:
Use probe_done and num_ports to call init and remove procedure
once per communication controller.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch enables padding of packets shorter than 64B in TX(set by default).
Disabling of padding causes crashes on MACCIATO board.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

A8K marvell SoC has two South Bridge communication controllers(CP0 and CP1).
Each communication controller has packet processor ports and MDIO.
On MACHIATOBin board ports from CP1 are connected to mdio on CP0.

Issue:
Wrong base address is assigned to MDIO interface during probe.

Fix:
Get MDIO address from PHY handler parent base address.

This should be refined in the future when MDIO driver is implemented.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch add GPIO configuration support in mvpp2x driver.
Driver will handle 10G SFP gpio reset and SFP TX disable. GPIO pins should
be set in device tree.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NKostya Porotchkin <kostap@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch fixes some remaining issues in the mvpp2 driver for the 10GB
support on port 0. These changes are:

- Incorrect PCS configuration
- Skip PHY configuration when no PHY is connected
- Skip GMAC configurations if 10G SFI mode set
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.

In the end we will have:

   1. dev_read_addr...()    - works on devices, supports flat/live tree
   2. devfdt_get_addr...()  - current functions, flat tree only
   3. of_get_address() etc. - new functions, live tree only

All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.

Note this involves changing some dead code - the imx_lpi2c.c file.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This patch adds a remove function to the mvpp2 ethernet driver which is
called before the OS is started, doing:

- Allocate the used buffers back from the buffer manager
- Stop the BM activity
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

As pointed out by Stefan Chulski, this variable is unused and should be
removed.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

On PPv2.2 we enable PHY polling, so we also need to configure the PHY
address in the specific PHY address rgisters.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Testing shows, that PHY polling needs to be enabled on Armada 7k/8k.
Otherwise ethernet transfers will not work correctly. PHY polling
is enabled per default after reset, so we do not need to specifically
enable it, but this makes it clearer.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Add a missing occurrance of PHY_INTERFACE_MODE_RGMII_ID, which should
be handled identical to PHY_INTERFACE_MODE_RGMII.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver for the missing port 0. This code is
mostly copied from the Marvell U-Boot version and was written by Stefan
Chulski. Please note that only SFI support have been added, as this
is the only interface that this code has been tested with. XAUI and
RXAUI support might follow at a later stage.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver. This code is mostly copied from the
Marvell U-Boot version and was written by Stefan Chulski. Please
note that only RGMII and SGMII support have been added, as these are
the only interfaces that this code has been tested with.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Read the "phy-speed" DT property to differentiate between 1 and 2.5GB
SGMII operations. Please note that its unclear right now, if this
DT property will be accepted in mainline Linux. If not, we need to
revisit this code and change it to use the accepted property.
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This patch does a bit of restructuring of the probe / init functions,
mainly to allow earlier register access as it is needed for the upcoming
GoP (Group of Ports) and NetC (Net Complex) code.
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This patch adds the PPv2.2 specific FIFO configuration to the mvpp2
driver. The RX FIFO packet data size is changed to the recommended
FIFO sizes. The TX FIFO configuration is newly added.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Currently, the naming of the ethernet ports is not handled correctly in
the multi-CP (Communication Processor) case. On Armada 8k, the slave-CP
also instantiates an ethernet controller with the same device ID's.
This patch now takes this into account and adds the required base-id
so that the slave-CP ethernet devices will be named "mvpp2-3 ...".

This patch also updates my Copyright notice to include 2017 as well.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This fixes problems noticed with the PPv2.2 A7k/8k port, when not all
elements of the descriptors had been cleared before use.
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This patch moves the base_probe function mvpp2_base_probe() from the
MISC driver to the ETH driver. When integrated in the MISC driver,
probe is called too early before the U-Boot ethernet infrastructure
(especially the MDIO / PHY interface) has been initialized. Resulting
in errors in mdio_register().
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

In U-Boot the MDIO / SMI support is integrated in the mvpp2 driver,
currently only supporting the 32bit platforms (Armada 37x). This patch
now adds the A7k/8k PPv2.2 MDIO support to that the phy / mii IF
can be used as well on these platforms.
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Now that the mvpp2 driver has been modified to accommodate the support
for PPv2.2, we can finally advertise this support by adding the
appropriate compatible string.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

In PPv2.1, we have a maximum of 8 RXQs per port, with a default of 4
RXQs per port, and we were assigning RXQs 0->3 to the first port, 4->7
to the second port, 8->11 to the third port, etc.

In PPv2.2, we have a maximum of 32 RXQs per port, and we must allocate
RXQs from the range of 32 RXQs available for each port. So port 0 must
use RXQs in the range 0->31, port 1 in the range 32->63, etc.

This commit adapts the mvpp2 to this difference between PPv2.1 and
PPv2.2:

- The constant definition MVPP2_MAX_RXQ is replaced by a new field
  'max_port_rxqs' in 'struct mvpp2', which stores the maximum number of
  RXQs per port. This field is initialized during ->probe() depending
  on the IP version.

- MVPP2_RXQ_TOTAL_NUM is removed, and instead we calculate the total
  number of RXQs by multiplying the number of ports by the maximum of
  RXQs per port. This was anyway used in only one place.

- In mvpp2_port_probe(), the calculation of port->first_rxq is adjusted
  to cope with the different allocation strategy between PPv2.1 and
  PPv2.2. Due to this change, the 'next_first_rxq' argument of this
  function is no longer needed and is removed.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This commit adjusts how the MVPP2_ISR_RXQ_GROUP_REG register is
configured, since it changed between PPv2.1 and PPv2.2.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The PPv2.2 unit is connected to an AXI bus on Armada 7K/8K, so this
commit adds the necessary initialization of the AXI bridge.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This commit handles a few miscellaneous differences between PPv2.1 and
PPv2.2 in different areas, where code done for PPv2.1 doesn't apply for
PPv2.2 or needs to be adjusted (getting the MAC address, disabling PHY
polling, etc.).

Changed by Stefan for U-Boot:
Since mvpp2_port_power_up() has multiple callers in U-Boot, the U-Boot
version of this patch does not remove this function but simply adds the
check for MVPP21 before the mvpp2_port_fc_adv_enable() call.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This commit adjusts the mvpp2 driver register mapping and access logic
to support PPv2.2, to handle a number of differences.

Due to how the registers are laid out in memory, the Device Tree binding
for the "reg" property is different:

- On PPv2.1, we had a first area for the common registers, and then one
  area per port.

- On PPv2.2, we have a first area for the common registers, and a
  second area for all the per-ports registers.

In addition, on PPv2.2, the area for the common registers is split into
so-called "address spaces" of 64 KB each. They allow to access the same
registers, but from different CPUs. Hence the introduction of cpu_base[]
in 'struct mvpp2', and the modification of the mvpp2_write() and
mvpp2_read() register accessors. For PPv2.1, the compatibility is
preserved by using an "address space" size of 0.

Changed by Stefan for U-Boot:
Since we don't support multiple CPUs in U-Boot, I've removed all the
code, macros and variables introduced in the Linux patch version for this.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

In PPv2.2, the MVPP2_RXQ_DESC_ADDR_REG and MVPP2_TXQ_DESC_ADDR_REG
registers have a slightly different layout, because they need to contain
a 64-bit address for the RX and TX descriptor arrays. This commit
adjusts those functions accordingly.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This commit modifies the mvpp2_defaults_set() function to not do the
loopback and FIFO threshold initialization, which are not needed for
PPv2.2.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The MVPP2_RXQ_CONFIG_REG register has a slightly different layout
between PPv2.1 and PPv2.2, so this commit adapts the functions modifying
this register to accommodate for both the PPv2.1 and PPv2.2 cases.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This commit adjusts the allocation and freeing of BM pools to support
PPv2.2. This involves:

- Checking that the number of buffer pointers is a multiple of 16, as
  required by the hardware.

- Adjusting the size of the DMA coherent area allocated for buffer
  pointers. Indeed, PPv2.2 needs space for 2 pointers of 64-bits per
  buffer, as opposed to 2 pointers of 32-bits per buffer in
  PPv2.1. The size in bytes is now stored in a new field of the
  mvpp2_bm_pool structure.

- On PPv2.2, getting the physical and virtual address of each buffer
  requires reading the MVPP2_BM_ADDR_HIGH_ALLOC to get the high order
  bits of those addresses. A new utility function
  mvpp2_bm_bufs_get_addrs() is introduced to handle this.

- On PPv2.2, releasing a buffer requires writing the high order 32 bits
  of the physical address to MVPP2_BM_PHY_VIRT_HIGH_RLS_REG. We no
  longer need to write the virtual address to MVPP2_BM_VIRT_RLS_REG.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This commit adds the definition of the PPv2.2 HW descriptors, adjusts
the mvpp2_tx_desc and mvpp2_rx_desc structures accordingly, and adapts
the accessors to work on both PPv2.1 and PPv2.2.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Since the format of the HW descriptors is different between PPv2.1 and
PPv2.2, this commit introduces an intermediate union, with for now
only the PPv2.1 descriptors. The bulk of the driver code only
manipulates opaque mvpp2_tx_desc and mvpp2_rx_desc pointers, and the
descriptors can only be accessed and modified through the accessor
functions. A follow-up commit will add the descriptor definitions for
PPv2.2.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

In preparation to the introduction for the support of PPv2.2 in the
mvpp2 driver, this commit adds a hw_version field to the struct
mvpp2, and uses the .data field of the DT match table to fill it in.

Having the MVPP21 and MVPP22 definitions available will allow to start
adding the necessary conditional code to support PPv2.2.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The PPv2.2 IP has a different TX and RX descriptor layout compared to
PPv2.1. In order to prepare for the introduction of PPv2.2 support in
mvpp2, this commit adds accessors for the different fields of the TX
and RX descriptors, and changes the code to use them.

For now, the mvpp2_port argument passed to the accessors is not used,
but it will be used in follow-up to update the descriptor according to
the version of the IP being used.

Apart from the mechanical changes to use the newly introduced
accessors, a few other changes, needed to use the accessors, are made:

- The mvpp2_txq_inc_put() function now takes a mvpp2_port as first
  argument, as it is needed to use the accessors.

- Similarly, the mvpp2_bm_cookie_build() gains a mvpp2_port first
  argument, for the same reason.

- In mvpp2_rx_error(), instead of accessing the RX descriptor in each
  case of the switch, we introduce a local variable to store the
  packet size.

- Similarly, in mvpp2_buff_hdr_rx(), we introduce a local "cookie"
  variable to store the RX descriptor cookie, rather than accessing
  it from the descriptor each time.

- In mvpp2_tx_frag_process() and mvpp2_tx() instead of accessing the
  packet size from the TX descriptor, we use the actual value
  available in the function, which is used to set the TX descriptor
  packet size a few lines before.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>