• T
    net: mvpp2: handle register mapping and access for PPv2.2 · 26a5278c
    Thomas Petazzoni 提交于
    This commit adjusts the mvpp2 driver register mapping and access logic
    to support PPv2.2, to handle a number of differences.
    
    Due to how the registers are laid out in memory, the Device Tree binding
    for the "reg" property is different:
    
    - On PPv2.1, we had a first area for the common registers, and then one
      area per port.
    
    - On PPv2.2, we have a first area for the common registers, and a
      second area for all the per-ports registers.
    
    In addition, on PPv2.2, the area for the common registers is split into
    so-called "address spaces" of 64 KB each. They allow to access the same
    registers, but from different CPUs. Hence the introduction of cpu_base[]
    in 'struct mvpp2', and the modification of the mvpp2_write() and
    mvpp2_read() register accessors. For PPv2.1, the compatibility is
    preserved by using an "address space" size of 0.
    
    Changed by Stefan for U-Boot:
    Since we don't support multiple CPUs in U-Boot, I've removed all the
    code, macros and variables introduced in the Linux patch version for this.
    Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
    Signed-off-by: NStefan Roese <sr@denx.de>
    Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
    26a5278c
mvpp2.c 122.0 KB