- 10 12月, 2018 1 次提交
-
-
由 Chris Packham 提交于
This was unintentionally removed when syncing with upstream. Signed-off-by: NChris Packham <judge.packham@gmail.com>
-
- 09 12月, 2018 3 次提交
-
-
git://git.denx.de/u-boot-marvell由 Tom Rini 提交于
- Sync DDR training with Marvell code for Armada 38x by Chris - Misc updates to Armada 38x Helios4 board by Aditya
-
由 Philipp Tomsich 提交于
The CRC16-CCITT checksum function is useful for space-constrained applications (such as obtaining a checksum across a 2KBit or 4KBit EEPROM) in boot applications. It has not been accessible from boot scripts until now (due to not having a dedicated command and not being supported by the hash infrstructure) limiting its applicability outside of custom commands. This adds the CRC16-CCITT (poly 0x1021, init 0x0) algorithm to the list of available hashes and adds a new crc16_ccitt_wd_buf() to make this possible. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> [trini: Fix building crc16.o for SPL/TPL] Signed-off-by: NTom Rini <trini@konsulko.com>
-
由 Philipp Tomsich 提交于
This merges the CRC16-CCITT headers into u-boot/crc.h to prepare for rolling CRC16 into the hash infrastructure. Given that CRC8, CRC32 and CRC32-C already have their prototypes in a single header file, it seems a good idea to also include CRC16-CCITT in the same. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
-
- 08 12月, 2018 19 次提交
-
-
由 Aditya Prayoga 提交于
Similar to Clearfog rev 2.1, GPIO 19 also used to reset onboard ethernet PHY. This patch depend on net: mvneta: Add GPIO configuration support [URL: https://patchwork.ozlabs.org/patch/1007736/] Signed-off-by: NAditya Prayoga <aditya@kobol.io> Reviewed-by: NStefan Roese <sr@denx.de> Tested-By: NDennis Gilmore <dgilmore@redhat.com> Reviewed-By: NDennis Gilmore <dgilmore@redhat.com> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Aditya Prayoga 提交于
Enable SPI flash support under U-Boot and SPL. The ENV size and offset, ported from U-Boot 2013.01 Marvell version: 2015_T1.0p16 To create U-Boot image for SPI flash, user would need to replace * CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC with CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI * CONFIG_ENV_IS_IN_MMC with CONFIG_ENV_IS_IN_SPI_FLASH Signed-off-by: NAditya Prayoga <aditya@kobol.io> Reviewed-by: NStefan Roese <sr@denx.de> Tested-By: NDennis Gilmore <dgilmore@redhat.com> Reviewed-By: NDennis Gilmore <dgilmore@redhat.com> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Aditya Prayoga 提交于
Remove unused I2C support in SPL and use simple_malloc functions to reduce SPL image size. Since Helios4 does not have any PCIe allocated on SerDes, remove PCI support. MTD layer on top of SPI flash is not needed, remove it also. Signed-off-by: NAditya Prayoga <aditya@kobol.io> Reviewed-by: NStefan Roese <sr@denx.de> Tested-By: NDennis Gilmore <dgilmore@redhat.com> Reviewed-By: NDennis Gilmore <dgilmore@redhat.com> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Aditya Prayoga 提交于
Make use of U-Boot's GPIO DM to control native GPIO and I2C IO expander. Signed-off-by: NAditya Prayoga <aditya@kobol.io> Reviewed-by: NStefan Roese <sr@denx.de> Tested-By: NDennis Gilmore <dgilmore@redhat.com> Reviewed-By: NDennis Gilmore <dgilmore@redhat.com> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Aditya Prayoga 提交于
Enable Marvell I2C driver and I2C IO expander. Set default bus to external I2C bus. Define I2C aliases in device tree so it can be recognized by the driver. Signed-off-by: NAditya Prayoga <aditya@kobol.io> Reviewed-by: NStefan Roese <sr@denx.de> Tested-By: NDennis Gilmore <dgilmore@redhat.com> Reviewed-By: NDennis Gilmore <dgilmore@redhat.com> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Aditya Prayoga 提交于
Store the environment before 1M into the block device. This constant is easier to remember, saves a little space, and is in line with what SolidRun's 2018.01-based fork does for the clearfog. Signed-off-by: NJosua Mayer <josua.mayer97@gmail.com> [ Aditya Prayoga: * Port forward] Signed-off-by: NAditya Prayoga <aditya@kobol.io> Reviewed-by: NStefan Roese <sr@denx.de> Tested-By: NDennis Gilmore <dgilmore@redhat.com> Reviewed-By: NDennis Gilmore <dgilmore@redhat.com> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Chris Packham 提交于
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-18.09 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. Specifically this syncs with commit 99d772547314 ("Bump mv_ddr to release armada-18.09.2"). The complete log of changes is best obtained from the mv-ddr-marvell.git repository but some relevant highlights are: ddr3: add missing txsdll parameter ddr3: fix tfaw timimg parameter ddr3: fix trrd timimg parameter merge ddr3 topology header file with mv_ddr_topology one mv_ddr: a38x: fix zero memory size scrubbing issue The upstream code is incorporated omitting the portions not relevant to Armada-38x and DDR3. After that a semi-automated step is used to drop unused features with unifdef find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT -UCONFIG_A3700 -UA3900 -UA80X0 \ -UA70X0 Signed-off-by: NChris Packham <judge.packham@gmail.com> Reviewed-by: NStefan Roese <sr@denx.de> Tested-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NStefan Roese <sr@denx.de>
-
git://git.denx.de/u-boot-sunxi由 Tom Rini 提交于
- Various axp209 fixes - Fixes for OLinuXino-A20-Lime2 / OLinuXino-A20-Lime2-eMMC
-
git://git.denx.de/u-boot-amlogic由 Tom Rini 提交于
Two fixes for the Amlogic Pinctrl driver : - bad usage of clrsetbits_le32 - bad pin definition for AXG Family
-
由 Andre Przywara 提交于
Now that the Allwinner port in the official mainline ARM Trusted Firmware repository has reached feature parity with the "legacy" ATF port, let's use the opportunity to update the Allwinner 64-bit build instructions. This changes: - Update ATF build instructions to use the mainline repo. - Add quick command lines for TL;DR people. - Mention Allwinner H6 build target. - Mention pre-built FEL binaries. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: NJagan Teki <jagan@openedev.com>
-
由 Priit Laes 提交于
The lime2 features a too large capacitor on the LDO3 output, which causes the PMIC to shutdown when enabling power. To be able to still boot up however, we must gradually enable power on LDO3 for this board. We do this by enabling both the inrush quirk and the maximum slope the AXP209 supports. Signed-off-by: NPriit Laes <plaes@plaes.org> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
-
由 Olliver Schinagl 提交于
The lime2 features a too large capacitor on the LDO3 output, which causes the PMIC to shutdown when enabling power. To be able to still boot up however, we must gradually enable power on LDO3 for this board. We do this by enabling both the inrush quirk and the maximum slope the AXP209 supports. Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl> Signed-off-by: NPriit Laes <plaes@plaes.org> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
-
由 Olliver Schinagl 提交于
Some boards feature a capacitance on LDO3's output that is too large, causing inrush currents which as a result, shut down the AXP209. This has been reported before, without knowing the actual cause. A fix appeared to be done with commit 0e6e34ac ("sunxi: Olimex A20 boards: Enable LDO3 and LDO4 regulators"). The description there is a bit misleading, the kernel does not hang during AXP209 initialization, the PMIC shuts down, causing voltages to drop and thus the whole system freezes. While the AXP209 does have the ability to ramp up the voltage slowly, to reduce these inrush currents, the voltage rate control (VRC) however is not applicable when switching on the LDO3 output. Only when going from an enabled lower voltage setting, to a higher voltage setting is the VRC in effect. To work around this problem, we set LDO3 to the lowest possible setting of 0.7 V if it was not yet enabled, and then let the VRC (if enabled) do its thing. It should be noted, that for some undocumented reason, there is a short delay needed between setting the LDO3 voltage register and enabling the power. One would expect that this delay ought to be just after enabling the output power at 0.7 V, but this did not work. Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl> Signed-off-by: NPriit Laes <plaes@plaes.org> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
-
由 Olliver Schinagl 提交于
The AXP209 LDO3 regulator supports voltage rate control, or can set a slew rate. This allows for the power to gradually rise up to the desired voltage, instead of spiking up as fast as possible. Reason to have this can be to reduce the inrush currents for example. There are 3 slopes to choose from, the default, 'none' is a voltage rise of 0.0167 V/uS, a 1.6 mV/uS and a 0.8 mV/uS voltage rise. In ideal world (where vendors follow the recommended design guidelines) this setting should not be enabled by default. Unless of course AXP209 crashes instead of reporting overcurrent condition as it normally should do in this case. Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl> Signed-off-by: NPriit Laes <plaes@plaes.org> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
-
由 Olliver Schinagl 提交于
The AXP209 has a few 'magisc-ish' values that are better served with clear defines. Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl> Signed-off-by: NPriit Laes <plaes@plaes.org> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
-
由 Olliver Schinagl 提交于
Use a define for the chip version mask on the axp209. Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl> Signed-off-by: NPriit Laes <plaes@plaes.org> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
-
由 Olliver Schinagl 提交于
Use the standard BIT() macro for bitfield definitions in headers. Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl> Signed-off-by: NPriit Laes <plaes@plaes.org> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
-
由 Olliver Schinagl 提交于
When we clear a pmic_bus bit, we do a read-modify-write operation. We waste some time however, by writing back the exact samea value that was already set in the chip. Let us thus only do the write in case data was changed. Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl> Signed-off-by: NPriit Laes <plaes@plaes.org> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
-
由 Olliver Schinagl 提交于
Currently during init, we enable all power, then enable the dram and after that check whether there was an error during power-up. This makes little sense, we should enable power and then check if power was brought up properly before we continue to initialize other things. This patch moves the DRAM init after the power failure check. Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl> Signed-off-by: NPriit Laes <plaes@plaes.org> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
-
- 07 12月, 2018 17 次提交
-
-
由 Tom Rini 提交于
- Various FAT fixes - Hardware spinlock uclass - DMA uclass - Various am335x fixes - DT resyncs for a number of TI platforms - stm32 updates
-
由 Felix Brack 提交于
This patch synchronizes the am33xx SoC specific files with those from Linux 4.20.0. Hence all board maintainers of am33xx based boards are on the cc list. The main purpose of this patch is to prevent further diverging of the dts files from U-Boot and those from Linux. It aims to set the stage for the synchronization of board specific dts files. Example: I'm the maintainer of the PDU001 board: once this patch is applied successfully I will make changes to the board specific dts file in Linux only and then post a patch with a copy of this exact dts file to U-Boot. This will make U-Boot and Linux remain in sync. The stumbling block of https://patchwork.ozlabs.org/patch/943627 was removed by the patch https://patchwork.ozlabs.org/patch/962428 from Lokesh Vutla (many thanks!). This omap-serial driver allows using the Linux am33xx.dtsi file in U-Boot. Other changes to dts and dtsi files made by this patch are mainly to prevent _new_ warnings during the build process. Especially the warning at pinmux@800 stating 'unnecessary #address-cells/#size-cells without "ranges" or child "reg"' was not removed. This warning is a good example showing the benefit of the synchronization: if it needs to be fixed it will be fixed in Linux and ported back to U-Boot. Buildman reports all 46 am33xx SoC based boards to build fine, with warnings of course. Nevertheless this patch should be tested thoroughly on as many boards as possible to prevent any collateral damage. Signed-off-by: NFelix Brack <fb@ltec.ch> Reviewed-by: NTom Rini <trini@konsulko.com>
-
由 Heiko Schocher 提交于
commit d6330064 ("spl: Add a define for SPL_TPL_PROMPT") changes the SPL/TPL banner from upper case into lower case. As SPL and TPL are three-letter acronyms and they are written in upper case, change it back to upper case. Signed-off-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NSimon Glass <sjg@chromium.org>
-
由 Adam Ford 提交于
There has been some natural evolution of the device tree, so resync with 4.20 Signed-off-by: NAdam Ford <aford173@gmail.com>
-
由 Adam Ford 提交于
Re-synce the device tree files from Linux 4.20 Signed-off-by: NAdam Ford <aford173@gmail.com>
-
由 Adam Ford 提交于
Re-sync with 4.20 due some some natural evolution. Signed-off-by: NAdam Ford <aford173@gmail.com>
-
由 Adam Ford 提交于
Migrate some small device tree fixes from Linux 4.20. Signed-off-by: NAdam Ford <aford173@gmail.com>
-
由 Adam Ford 提交于
There have been a few fixes to the device trees, so this re-syncs the dts/dtsi files with Linux Signed-off-by: NAdam Ford <aford173@gmail.com>
-
由 Felix Brack 提交于
This patch adds code missing when CONFIG_DEBUG_UART_OMAP is enabled as early debugging UART. The code is basically copied from the ns16550 driver. Signed-off-by: NFelix Brack <fb@ltec.ch>
-
由 Alexey Brodkin 提交于
Build tested in Travis, see: https://travis-ci.org/abrodkin/u-boot/jobs/462808237Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
-
由 Adam Ford 提交于
The DTS file for the AM3517 had the incorrect CD polarity. Resync with the fixed DTS file from Linux. Signed-off-by: NAdam Ford <aford173@gmail.com>
-
由 Frank Wunderlich 提交于
Hi, setting active menuitem currently can be outside of menu which results in invisible selection attached Patch fixes this regards Frank >From 1d9c4cb8b3e2dd9b0a7a6a2d4a21684d0a099dbf Mon Sep 17 00:00:00 2001 From: Frank Wunderlich <frank-w@public-files.de> Date: Sun, 2 Dec 2018 11:23:53 +0100 Subject: [PATCH] ensure active menuitem is inside menu if active menuitem is defined via environment var it can be outside the menu (>=menuitem-count) this patch resets this definition back to 0 Signed-off-by: NFrank Wunderlich <frank-w@public-files.de>
-
由 Patrice Chotard 提交于
Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
-
由 Patrice Chotard 提交于
As all STM32 SoCs supports CONFIG_CLK flag, it becomes useless in this driver, remove it. Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
-
由 Patrice Chotard 提交于
To allow access to this define by other driver, move it into gpio.h Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
-
由 Patrice Chotard 提交于
In some STM32 SoC packages, GPIO bank has not always 16 gpios. Several cases can occur, gpio hole can be located at the beginning, middle or end of the gpio bank or a combination of these 3 configurations. For that, gpio bindings offer the gpio-ranges DT property which described the gpio bank mapping. Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
-
由 Patrice Chotard 提交于
Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
-