Signed-off-by: NYegor Yefremov <yegorslists@googlemail.com>

According to errata the AM335x device does not support internal delay
mode, so RGMII1_IDMODE and RGMII2_IDMODE must be set to 1.
Signed-off-by: NYegor Yefremov <yegorslists@googlemail.com>

Added macros to read SOM information from the I2C
EEPROM.
Signed-off-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NStefano Babic <sbabic@denx.de>

The reset procedure works on watchdog timer while before it was modifying
TIMER_1 registers.
Tested on DM365.
Signed-off-by: NDavide Bonfanti <davide.bonfanti@bticino.it>

Added posted writes (read after writes) to effect the
change immediately for channel confiuration and channel
enable register

Disable the channel to purge receieve data in TX_ONLY
mode transfer otherwise rx data will get affected by
the next immediate RX_ONLY mode transfer

Wait for the EOT bit to be set after last byte has been
loaded to TX shift register in the the TX_ONLY mode.This
ensures TX data has been completely shifted out

Disable the channel in RX_ONLY mode before reading the
last data from  RXX register to prevent the SPI slave
to transmit next word
Signed-off-by: NAjoy Kumar Das <akdas75@yahoo.in>
Cc: Tom Rini <trini@ti.com>
Cc: jacopo mondi <j.mondi@voltaelectronics.com>

DMM_LISA_MAP registers program whether memory is mapped
on particular EMIF or not. Irrespective of these registers
EMIF is getting configured. Correcting the same.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Git commit d417d1db replaced the
omap-common file reset.S with reset.c, but the Makefile was not
adjusted for that.
Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca>

No functional changes, simply for readability.
Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca>

No functional changes, just more comments for readability when a
preprocessor check spans more than a few lines, and for consistency.
Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca>

Instead of passing individual registers by value to board_get_mem_timings,
pass a board_mem_timings structure pointer for the board files to fill in.
Pass same structure pointer to write_sdrc_timings.  This saves about
90 bytes of space in SPL.
Signed-off-by: NPeter Barada <peter.barada@logicpd.com>

Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca>

Enable booting from NAND support from AM335x boards as well as
environment in NAND.
Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>

AM33XX with BCH8 can't work with nand_spl_simple correctly
because custom read_page implementation is required for proper
syndrome generation.

This simple driver mostly duplicates nand_spl_simple but has
nand_read_page changed to suit our needs.
Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>

This patch adds support for BCH8 error correction code to omap_gpmc
driver. We use GPMC to generate codes/syndromes but we need ELM to find
error locations from given syndrome.
Signed-off-by: NMansoor Ahamed <mansoor.ahamed@ti.com>
[ilya: merge it with omap_gpmc driver, some fixes and cleanup]
Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>

AM33XX has Error Location Module (ELM) that can be used in conjuction
with GPMC controller to implement BCH codes fully in hardware.
This code is mostly taken from arago tree.
Signed-off-by: NMansoor Ahamed <mansoor.ahamed@ti.com>
Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>

Enable NAND support for AM335X boards.
Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>

TI AM33XX has the same GPMC controller as OMAP3 so we could just use the
existing omap_gpmc driver. This patch adds adds required
definitions/intialization.
Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>

Add NAND pins mux settings for AM335X devices. Enable NAND pins
for AM335X EVM board.
Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>

Include asm/arch/sys_proto.h for gpmc_init prototype.
Without this we get a warning while building for AM335x.
Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>

These GPMC_CS defines are a leftover from prior gpmc_init(). Commit 187af954
removed the need for these definitions but missed to remove them.
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>

The POWER_DCLIMITS_NEGLIMIT_OFFSET bit in mx28 power supply block is
not called POWER_DCLIMITS_NETLIMIT_OFFSET, but POWER_DCLIMITS_NEGLIMIT_OFFSET.
Correct the name in the header file.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

The POWER_MINPWR_VBG_OFF bit in mx28 power supply block is not called
POWER_MINPWR_FBG_OFF, but POWER_MINPWR_VBG_OFF. Correct the name in the
header file.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

Modify tegra-common-post.h's BOOTCOMMAND definition to use the generic
filesystem command load rather than separate fatload and ext2load.
This removes the need to iterate over supported filesystem types in the
boot command.

This requires editing all board config headers to enable the new
commands. The now-unused commands are left enabled to assue backwards
compatibility with any user scripts. Boards (all from Avionic Design)
which define custom BOOTCOMMAND values are not affected.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
tegra generic fs cmds fixup
Signed-off-by: NTom Warren <twarren@nvidia.com>

The NAND defines ended up before this include file, but should be after
it, so it doesn't become a post-pre-NAND.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Now that we are using the new CONFIG_SYS_NAND_SELF_INIT setup, we don't
need CONFIG_SYS_NAND_BASE. Punt it.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Harmony contains an SD slot with all 8 bits routed. This allows plugging
in an eMMC-chip-in-SD-form-factor.

Seaboard/Springbank/Ventana/AC100 all have an eMMC chip with all 8 bits
hooked up.

Now that the U-Boot eMMC code fully supports 8-bit operation, initialize
those ports as 8-bit instead of 4-bit to improve performance.

Whistler was already registering its ports as 8-bit.

TrimSlice doesn't have any 8-bit ports.

I don't have any Avionic Design boards nor the Colibri board to test with.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

If a board has all 8 data lines routed, the SD/MMC controller can still
operate in 4-bit (or presumably even 1-bit) mode. Adjust Tegra's MMC
driver to report the 4-bit capability even for 8-bit slots.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Add support for CONSOLE_MUX to tegra-kbc driver.  This requires
adding a flag to struct keyb to know the driver has already been
initialized so if we try to initialize it again we can just return
success.  Also call into iomux_doenv() from drv_keyboard_init to
re-evaluate the stdin string.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

TrimSlice's USB1 port has two purposes; it either acts as a device port
hosting Tegra's USB recovery protocol, or acts as a host port connected
to the internal USB->SATA bridge chip, which may in turn be connected to
an SSD or HDD. Add the appropriate device tree and board configuration
options to enable this port as a host port, and route the port to the
SATA bridge using the VBUS GPIO.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Enable the Seaboard's 16-bit LCD and use it as the console.
Signed-off-by: NMayuresh Kulkarni <mkulkarni@nvidia.com>
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

When the cursor position gets to the end of the LCD console we normally
scroll by one line. This adds an option to increase that value.

Console scrolling is often slow, and if a large amount of output is
being sent, increasing this option to 10 or so will speed things up
considerably.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

The Seaboard has a 1366x768 16bpp LCD. The backlight is controlled
by one of the PWMs.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Add support for selecting the required cache mode for the LCD:
off, write-through or write-back.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

For tegra we want to enable the cache for the LCD. This is easier if
we can avoid using L2 page tages, so align the LCD to a section
boundary.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

This provides an option for the LCD to flush the dcache after each update
(puts, scroll or clear).
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

The normal alignment is PAGE_SIZE, but if this is defined, we can support
other alignments.

The motivation for this change is to make the display section-aligned on
ARM so that we can easily turn off data caching for the frame buffer region
without resorting to level 2 page tables.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Add support for adjusting the L1 cache behavior by updating the MMU
configuration. The mmu_set_region_dcache_behaviour() function allows
drivers to make these changes after the MMU is set up.

It is implemented only for ARMv7 at present.

This is needed for LCD support, where we want to make the LCD frame buffer
write-through (or off) rather than write-back.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Add calls to the LCD driver from Nvidia board code.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>