OMAP3+: reset: Create a common reset layer.

The reset.S has the function to do a warm reset on OMAP
based socs. Moving this to a reset.c file so that this
acts a common layer to add any reset related functionality
for the future.
Signed-off-by: NR Sricharan <r.sricharan@ti.com>

arch/arm/cpu/armv7/omap-common/reset.S → arch/arm/cpu/armv7/omap-common/reset.c

 /*
- * Copyright (c) 2009 Samsung Electronics.
- * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * Common layer for reset related functionality of OMAP based socs.
+ *
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -20,19 +25,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-
 #include <config.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <linux/compiler.h>
 
-.global reset_cpu
-reset_cpu:
-	ldr	r1, rstctl			@ get addr for global reset
-						@ reg
-	ldr	r3, rstbit			@ sw reset bit
-	str	r3, [r1]			@ force reset
-	mov	r0, r0
-_loop_forever:
-	b	_loop_forever
-rstctl:
-	.word	PRM_RSTCTRL
-rstbit:
-	.word	PRM_RSTCTRL_RESET
+void __weak reset_cpu(unsigned long ignored)
+{
+	writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
+}

arch/arm/include/asm/arch-omap3/cpu.h

@@ -474,12 +474,11 @@ struct prm {
 	u8 res3[0x1c];
 	u32 clksrc_ctrl;	/* 0x1270 */
 };
-#else /* __ASSEMBLY__ */
-#define PRM_RSTCTRL		0x48307250
-#define PRM_RSTCTRL_RESET	0x04
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 
+#define PRM_RSTCTRL		0x48307250
+#define PRM_RSTCTRL_RESET	0x04
 #define SYSCLKDIV_1		(0x1 << 6)
 #define SYSCLKDIV_2		(0x1 << 7)
 

arch/arm/include/asm/arch-omap4/cpu.h

@@ -168,4 +168,15 @@ struct watchdog {
 #define OMAP_GPIO_CLEARDATAOUT		0x0190
 #define OMAP_GPIO_SETDATAOUT		0x0194
 
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE		0x4A306000
+#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL		PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET	0x01
+
 #endif /* _CPU_H */

arch/arm/include/asm/arch-omap4/omap.h

@@ -101,17 +101,6 @@
 #define TCLR_AR			(0x1 << 1)
 #define TCLR_PRE		(0x1 << 5)
 
-/*
- * PRCM
- */
-
-/* PRM */
-#define PRM_BASE		0x4A306000
-#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
-
-#define PRM_RSTCTRL		PRM_DEVICE_BASE
-#define PRM_RSTCTRL_RESET	0x01
-
 /* Control Module */
 #define LDOSRAM_ACTMODE_VSET_IN_MASK	(0x1F << 5)
 #define LDOSRAM_VOLT_CTRL_OVERRIDE	0x0401040f

arch/arm/include/asm/arch-omap5/cpu.h

@@ -172,4 +172,15 @@ struct watchdog {
 #define OMAP_GPIO_CLEARDATAOUT		0x0190
 #define OMAP_GPIO_SETDATAOUT		0x0194
 
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE		0x4AE06000
+#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL		PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET	0x01
+
 #endif /* _CPU_H */

arch/arm/include/asm/arch-omap5/omap.h

@@ -98,17 +98,6 @@
 #define TCLR_AR			(0x1 << 1)
 #define TCLR_PRE		(0x1 << 5)
 
-/*
- * PRCM
- */
-
-/* PRM */
-#define PRM_BASE		0x4AE06000
-#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
-
-#define PRM_RSTCTRL		PRM_DEVICE_BASE
-#define PRM_RSTCTRL_RESET	0x01
-
 /* Control Module */
 #define LDOSRAM_ACTMODE_VSET_IN_MASK	(0x1F << 5)
 #define LDOSRAM_VOLT_CTRL_OVERRIDE	0x0401040f