This adds a define for the bit in rstmgr's ctrl regiser that issues
a cold reset (we had a define for the warm reset bit only) in preparation
for a proper sysrese driver.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Series changes: 2
- separate this patch to the register descriptions from the actual
  sysreset driver patch

The 'dwmac_socfpga' ETH driver can now get the MACs out of reset
via the socfpga reset driver and can set PHY mode via syscon.

This means we can now remove the ad-hoc code to do this from
arch/arm/mach-socfpga.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Add Reset Manager driver support for Stratix SoC
Signed-off-by: NChin Liang See <chin.liang.see@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

The EMAC reset and PHY mode configuration was never working on the
Arria10 SoC, fix this. This patch pulls out the common code into
misc.c and passes the SoC-specific function call in as a function
pointer.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>

This was never used, is not used anywhere and is just in the way
by adding annoying ifdeffery. Get rid of it.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: NTom Rini <trini@konsulko.com>

Add reset driver support for Arria 10.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Define the NAND reset bit and fix the ordering of the macros.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

The Cyclone V Hard Processor System Technical Reference Manual in the
chapter about the Reset Manager Module Address Map stats that the offset
of the tstscratch register ist 0x54 not 0x24.

Cyclone V Hard Processor System Technical Reference Manual cv_5v4 2015.11.02
page 3-17 Reset Manager Module Address Map
Signed-off-by: NPhilipp Rosenberger <ilu@linutronix.de>

The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register,
not the mpumodrst. So the bank for these reset bits should be 1, not 0.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

Add SDMMC, QSPI and DMA reset defines. These are needed by SPL
so that we can boot from SD card and QSPI.
Signed-off-by: NMarek Vasut <marex@denx.de>

Add socfpga_per_reset_all() function to reset all peripherals
but the L4 watchdog. This is needed in the SPL.
Signed-off-by: NMarek Vasut <marex@denx.de>

Replace all those ad-hoc reset functions, which were all copies
of the same invocation of clrbits_le32() anyway, with one single
unified function, socfpga_per_reset(), with necessary parameters.
Signed-off-by: NMarek Vasut <marex@denx.de>

Implement function socfpga_per_reset(), which allows asserting or
de-asserting reset of each reset manager peripheral in a unified
manner. Use this function throughout reset manager.
Signed-off-by: NMarek Vasut <marex@denx.de>

Implement macro SOCFPGA_RESET(name), which produces an abstract
reset number. Implement macros which allow extracting the reset
offset in permodrstN register and which permodrstN register the
reset is located in from this abstract reset number. Use these
macros throughout the reset manager.
Signed-off-by: NMarek Vasut <marex@denx.de>

Define two missing reset manager registers, which are in the
SoCFPGA CV datasheet.
Signed-off-by: NMarek Vasut <marex@denx.de>

Move headers to mach-socfpga as well.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These functions will be needed for use by the SPL for enabling the
console and sdram initialization.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: NMarek Vasut <marex@denx.de>
Acked-by: NPavel Machek <pavel@denx.de>

This function will be needed by the upcoming Designware master SPI
driver. As the SPI master controller is held in reset by the current
Preloader implementation. So we need to release the reset for the
driver to communicate with the controller.

This function is called from arch_early_init_r() if the SPI
driver is enabled.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>

Add function to enable and disable FPGA bridges. This code is used
by the FPGA manager to disable the bridges before programming the
FPGA and will later be also used by the initialization code for the
chip to put the chip into well defined state during startup.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: NPavel Machek <pavel@denx.de>

Add functions to reset the EMAC ethernet blocks. We cannot handle
two EMAC ethernet blocks yet, therefore the ifdefs. Once there is
hardware using both EMAC blocks, this ifdef will have to go.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: NPavel Machek <pavel@denx.de>

This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by: NPavel Machek <pavel@denx.de>
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h
    Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)

Consolidating reset code into reset_manager.c. Also
separating reset configuration for virtual target and
real hardware Cyclone V development kit
Signed-off-by: NChin Liang See <clsee@altera.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>

Signed-off-by: NWolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: NTom Rini <trini@ti.com>

Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Signed-off-by: NChin Liang See <clsee@altera.com>
Signed-off-by: NPavel Machek <pavel@denx.de>
Reviewed-by: NMarek Vasut <marex@denx.de>
Acked-by: NTom Trini <trini@ti.com>
Cc: Wolfgang Denx <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefan Roese <sr@denx.de>
----
v8: Remove no_return attribute for reset_cpu

Based on v2012.10-rc2

Most code can be shared between i.MX23 and i.MX28 as both are from
i.MXS family; this source directory structure makes easy to share code
among them.
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
Acked-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>

Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Acked-by: NAndy Fleming <afleming@gmail.com>

This patch supports:
- Timers
- Debug UART
- Clock
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>

Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

This patch adds support for DaVinci DM365 SOC.
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>

Add some basic declarations for DaVinci DM355/DM350/DM335 support,
keyed on CONFIG_SOC_DM355.  (DM35X isn't quite right because the
DM357 is very different; while the DM355 is like a DM355 without
the MPEG/JPEG coprocessor).

These have different peripherals than the DM6446, and some of
the peripherals are at different addresses.  Notably for U-Boot,
there's no EMAC, and the NAND controller address is different
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>

ARM DaVinci: Move common functions to board/davinci/common.
Signed-off-by: NHugo Villeneuve <hugo.villeneuve@lyrtech.com>

add support for USB-based console
(enable with "setenv stdout usbtty; setenv stdin usbtty")