- 14 4月, 2018 16 次提交
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由 Marek Vasut 提交于
Synchronize the naming with Linux, call the common code TMIO. No functional change. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Drop the CONFIG_MMC_RENESAS_TUNING symbol from Gen3 configs. This symbol is no longer used after the Matsushita SDHI driver, instead the renesas-sdhi driver uses CONFIG_MMC_HS200_SUPPORT to discern whether the tuning support should be compiled in. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -- V2: Submit this on top of configs which are actually in mainline
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由 Marek Vasut 提交于
There is currently no use for building the SPL anymore, since the SPI loader can easily be replaced by TPL and TPL does load U-Boot directly. Upgrade TPL to SPL and replace what used to be SPL with it. This way we build the U-Boot sources only twice, not thrice. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Shrink the TPL by using tiny printf and tiny memset by default. This removes the biggest symbol -- vsnprintf_internal -- from the TPL and reduces the text segment by about 2 kiB. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
The H2 Stout port was broken since some time. This patch updates the H2 Stout port to use modern frameworks, DM, DT probing, SPL and TPL for the preloading and puts it on par with the M2 Porter board. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
The offset of CSWCRx starts at 0x30, fix this. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
The H2 Stout uses SCIFA0 for serial console, make sure it is available very early on when probing from DT. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add the SCIFA0 address entry so it can be used in TPL if needed due to size restrictions. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add compatible strings for R8A7790, R8A7793 and R8A7794, since the contemporary DTs use those don't have a generic match value. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
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由 Marek Vasut 提交于
The initconst is not used in U-Boot, drop it. The r8a7790_crit_mod_clks is also not used in U-Boot, so drop it too. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Heinrich Schuchardt 提交于
With CONFIG_ARMV7_BOOT_SEC_DEFAULT=y a syntax error occurs. Add the missing semicolon. Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
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由 Tom Rini 提交于
- For am335x_pdu001 we do not want the CPSW driver, drop it - Re-sync the defconfig for am43xx_evm_rtconly as it came in after the patch that converted CPSW to Kconfig was posted but before it was applied. - Drop empty section / comments from pengwyn - Drop empty section / comments from baltos and drop unused CONFIG_SPL_NET_VCI_STRING (it does not enable CONFIG_SPL_NET_SUPPORT currently and SPL_NET_VCI_STRING has been migrated already). Cc: Felix Brack <fb@ltec.ch> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Yegor Yefremov <yegorslists@googlemail.com> Cc: Lothar Felten <lothar.felten@gmail.com> Fixes: f02b8d17 ("Migrate CONFIG_DRIVER_TI_CPSW to Kconfig") Signed-off-by: NTom Rini <trini@konsulko.com> Reviewed-by: NFelix Brack <fb@ltec.ch> Tested-by: NFelix Brack <fb@ltec.ch>
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由 Vasyl Vavrychuk 提交于
Without armv8_setup_psci register VBAR_EL3 is not set up property which makes SMC calls jump to invalid location. smp_kick_all_cpus is required to make slave cpus leave gic_wait_for_interrupt. Without this they will never pursue booting process. Fix was applied to the two ways of booting VxWorks: bootvx and bootm commands. This implementation is very similar to what is done in boot_jump_linux in arch/arm/lib/bootm.c file. Tested on VxWorks 7 release SR0520 2017-12-08 Intel Stratix 10 SX SoC Development Kit board. Signed-off-by: NVasyl Vavrychuk <vasyl.vavrychuk@globallogic.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Christian Gmeiner 提交于
Make it possible to use gcc code coverage analysis. v1 -> v2: - Kconfig: remove not needed 'default n' - Makefile: use consistent spacing Signed-off-by: NChristian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Jean-Jacques Hiblot 提交于
Those options are required to enable support for SATA on DRA7 platforms. Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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由 Jean-Jacques Hiblot 提交于
The dwc_ahci has been broken for quite some time now. The breakage has been introduced by the series "dm: scsi: Enhance SCSI support for driver model" Use ahci_bind_scsi() and ahci_probe_scsi() to properly bind and probe the driver. Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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- 13 4月, 2018 2 次提交
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- 12 4月, 2018 22 次提交
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由 Marek Vasut 提交于
The Gen3 kernel images are often above 8 MiB, increase the maximum kernel size to 64 MiB to future-proof it, just like many other ARM64 boards do. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Fix up the memory map on Gen3 to match datasheet properly. This simplifies the memory map setup as well, since we do no longer need this massive complexity. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
The QSPI controller on RCar Gen2 has 32byte FIFO. Instead of doing the SPI transmission 1 byte at time, if there is a 32byte chunk of data to be transferred, fill the FIFO completely and then transfer the data to/from the FIFO. This increases the SPI NOR access speed significantly. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Marek Vasut 提交于
Replace the ad-hoc endless loops with wait_for_bit() with reasonable timeout. Note that the loops had internal 10uS delays, although there is no reason for those on this HW, so they are dropped. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Marek Vasut 提交于
Waiting for SPBDCR == 1 is not required and is covered by the subsequent wait for SPSR_SPRFF, so drop this. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Marek Vasut 提交于
Just replace unsigned {char,short,long} with u{8,16,32}, no functional change. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Marek Vasut 提交于
Add driver for the RPC block in SPI-flash mode. This driver allows access to a SPI NOR flash attached to the RPC block and does not support RPC in Hyperflash mode. Note that this block is extremely selective when communicating with the SPI NOR. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add driver for the RPC block in Hyperflash mode. This driver allows access to a CFI Hyperflash attached to the RPC block and does not support RPC in SPI mode. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
The IP requires some time to recuperate after the IO pin properties were changed. Add a delay to assure this. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Fix minor rebase omission, the else was missing which triggered two accesses to the register on 64bit variant of the IP. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Make sure to wait for the command to complete altogether, including the trailing 8 clock cycles. This prevents the driver for accidentally writing the CMD register too fast before the previous command fully completed. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
The HOST_MODE register must be set to 0 when the IP is operated in 16bit mode, otherwise 16bit access to the data FIFO may fail. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
There are only a few registerse used in the 16bit mode which are 32bit internally. Special-case only those in the IO accessors and always write both halves. Any other register access is protected from accidentally overwriting neighboring register. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Enable the HS200 on RCar Gen3 platforms, since the SDHI core supports it. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add code for PHY tuning required for SDR104/HS200 support on Renesas RCar. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Export the matsu_sd_{read,write}l() common register access functions, so that they can be used by other drivers sharing the common code. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Factor out the regulator handling into set_ios and add support for selecting pin configuration based on the voltage to support UHS modes. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Handle the controller version even if quirks are set. The controller in Renesas Gen3 SoCs does provide the version register, which indicates a controller v10 and the controller does support internal DMA and /1024 divider. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Handle bus width 0 as 1-bit bus to assure valid content of MATSU_SD_OPTION register WIDTH field. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
The DMA READ completion flag position differs on Socionext and Renesas SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on them. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
On the Renesas version of the IP, the /1 divider is realized by setting the clock register [7:0] to 0xff instead of setting bit 10 of the register. Check the quirk and handle accordingly. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Add a quirk to identify that the controller is Renesas RCar variant of the Matsushita SD IP and another quirk indicating it can support Renesas RCar HS200/HS400/SDR104 modes. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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