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提交 cb0b6b03 编写于 作者: M Marek Vasut 提交者： Marek Vasut
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mmc: tmio: Rename Matsushita to TMIO 

Synchronize the naming with Linux, call the common code TMIO.
No functional change.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
上级 76af7e51
展开全部 隐藏空白更改
内联 并排
Showing with 422 addition and 422 deletion
drivers/mmc/Makefile
浏览文件 @ cb0b6b03
......@@ -62,6 +62,6 @@ obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o
obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o
obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
obj-$(CONFIG_MMC_UNIPHIER) += matsushita-common.o uniphier-sd.o
obj-$(CONFIG_RENESAS_SDHI) += matsushita-common.o renesas-sdhi.o
obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o
obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o
obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o
drivers/mmc/matsushita-common.h 已删除 100644 → 0
浏览文件 @ 76af7e51
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MATSUSHITA_COMMON_H__
#define __MATSUSHITA_COMMON_H__
#define MATSU_SD_CMD 0x000 /* command */
#define MATSU_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
#define MATSU_SD_CMD_MULTI BIT(13) /* multiple block transfer */
#define MATSU_SD_CMD_RD BIT(12) /* 1: read, 0: write */
#define MATSU_SD_CMD_DATA BIT(11) /* data transfer */
#define MATSU_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
#define MATSU_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */
#define MATSU_SD_CMD_RSP_NONE (3 << 8)/* response: none */
#define MATSU_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */
#define MATSU_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */
#define MATSU_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */
#define MATSU_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */
#define MATSU_SD_ARG 0x008 /* command argument */
#define MATSU_SD_STOP 0x010 /* stop action control */
#define MATSU_SD_STOP_SEC BIT(8) /* use sector count */
#define MATSU_SD_STOP_STP BIT(0) /* issue CMD12 */
#define MATSU_SD_SECCNT 0x014 /* sector counter */
#define MATSU_SD_RSP10 0x018 /* response[39:8] */
#define MATSU_SD_RSP32 0x020 /* response[71:40] */
#define MATSU_SD_RSP54 0x028 /* response[103:72] */
#define MATSU_SD_RSP76 0x030 /* response[127:104] */
#define MATSU_SD_INFO1 0x038 /* IRQ status 1 */
#define MATSU_SD_INFO1_CD BIT(5) /* state of card detect */
#define MATSU_SD_INFO1_INSERT BIT(4) /* card inserted */
#define MATSU_SD_INFO1_REMOVE BIT(3) /* card removed */
#define MATSU_SD_INFO1_CMP BIT(2) /* data complete */
#define MATSU_SD_INFO1_RSP BIT(0) /* response complete */
#define MATSU_SD_INFO2 0x03c /* IRQ status 2 */
#define MATSU_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */
#define MATSU_SD_INFO2_CBSY BIT(14) /* command busy */
#define MATSU_SD_INFO2_SCLKDIVEN BIT(13) /* command setting reg ena */
#define MATSU_SD_INFO2_BWE BIT(9) /* write buffer ready */
#define MATSU_SD_INFO2_BRE BIT(8) /* read buffer ready */
#define MATSU_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */
#define MATSU_SD_INFO2_ERR_RTO BIT(6) /* response time out */
#define MATSU_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */
#define MATSU_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */
#define MATSU_SD_INFO2_ERR_TO BIT(3) /* time out error */
#define MATSU_SD_INFO2_ERR_END BIT(2) /* END bit error */
#define MATSU_SD_INFO2_ERR_CRC BIT(1) /* CRC error */
#define MATSU_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */
#define MATSU_SD_INFO1_MASK 0x040
#define MATSU_SD_INFO2_MASK 0x044
#define MATSU_SD_CLKCTL 0x048 /* clock divisor */
#define MATSU_SD_CLKCTL_DIV_MASK 0x104ff
#define MATSU_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
#define MATSU_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
#define MATSU_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
#define MATSU_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
#define MATSU_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
#define MATSU_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
#define MATSU_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
#define MATSU_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
#define MATSU_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
#define MATSU_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
#define MATSU_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
#define MATSU_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */
#define MATSU_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
#define MATSU_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
#define MATSU_SD_SIZE 0x04c /* block size */
#define MATSU_SD_OPTION 0x050
#define MATSU_SD_OPTION_WIDTH_MASK (5 << 13)
#define MATSU_SD_OPTION_WIDTH_1 (4 << 13)
#define MATSU_SD_OPTION_WIDTH_4 (0 << 13)
#define MATSU_SD_OPTION_WIDTH_8 (1 << 13)
#define MATSU_SD_BUF 0x060 /* read/write buffer */
#define MATSU_SD_EXTMODE 0x1b0
#define MATSU_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
#define MATSU_SD_SOFT_RST 0x1c0
#define MATSU_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */
#define MATSU_SD_VERSION 0x1c4 /* version register */
#define MATSU_SD_VERSION_IP 0xff /* IP version */
#define MATSU_SD_HOST_MODE 0x1c8
#define MATSU_SD_IF_MODE 0x1cc
#define MATSU_SD_IF_MODE_DDR BIT(0) /* DDR mode */
#define MATSU_SD_VOLT 0x1e4 /* voltage switch */
#define MATSU_SD_VOLT_MASK (3 << 0)
#define MATSU_SD_VOLT_OFF (0 << 0)
#define MATSU_SD_VOLT_330 (1 << 0)/* 3.3V signal */
#define MATSU_SD_VOLT_180 (2 << 0)/* 1.8V signal */
#define MATSU_SD_DMA_MODE 0x410
#define MATSU_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
#define MATSU_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
#define MATSU_SD_DMA_CTL 0x414
#define MATSU_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
#define MATSU_SD_DMA_RST 0x418
#define MATSU_SD_DMA_RST_RD BIT(9)
#define MATSU_SD_DMA_RST_WR BIT(8)
#define MATSU_SD_DMA_INFO1 0x420
#define MATSU_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete (uniphier) */
#define MATSU_SD_DMA_INFO1_END_RD BIT(17) /* DMA from device is complete (renesas) */
#define MATSU_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
#define MATSU_SD_DMA_INFO1_MASK 0x424
#define MATSU_SD_DMA_INFO2 0x428
#define MATSU_SD_DMA_INFO2_ERR_RD BIT(17)
#define MATSU_SD_DMA_INFO2_ERR_WR BIT(16)
#define MATSU_SD_DMA_INFO2_MASK 0x42c
#define MATSU_SD_DMA_ADDR_L 0x440
#define MATSU_SD_DMA_ADDR_H 0x444
/* alignment required by the DMA engine of this controller */
#define MATSU_SD_DMA_MINALIGN 0x10
struct matsu_sd_plat {
struct mmc_config cfg;
struct mmc mmc;
};
struct matsu_sd_priv {
void __iomem *regbase;
unsigned long mclk;
unsigned int version;
u32 caps;
#define MATSU_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
#define MATSU_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
#define MATSU_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
#define MATSU_SD_CAP_64BIT BIT(3) /* Controller is 64bit */
#define MATSU_SD_CAP_16BIT BIT(4) /* Controller is 16bit */
#define MATSU_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas RCar version of IP */
#define MATSU_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas RCar version of IP */
#define MATSU_SD_CAP_RCAR_UHS BIT(7) /* Renesas RCar UHS/SDR modes */
#define MATSU_SD_CAP_RCAR \
(MATSU_SD_CAP_RCAR_GEN2 | MATSU_SD_CAP_RCAR_GEN3)
#ifdef CONFIG_DM_REGULATOR
struct udevice *vqmmc_dev;
#endif
};
int matsu_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data);
int matsu_sd_set_ios(struct udevice *dev);
int matsu_sd_get_cd(struct udevice *dev);
int matsu_sd_bind(struct udevice *dev);
int matsu_sd_probe(struct udevice *dev, u32 quirks);
u32 matsu_sd_readl(struct matsu_sd_priv *priv, unsigned int reg);
void matsu_sd_writel(struct matsu_sd_priv *priv,
u32 val, unsigned int reg);
#endif /* __MATSUSHITA_COMMON_H__ */
drivers/mmc/renesas-sdhi.c
浏览文件 @ cb0b6b03
......@@ -16,7 +16,7 @@
#include <power/regulator.h>
#include <asm/unaligned.h>
#include "matsushita-common.h"
#include "tmio-common.h"
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
......@@ -38,86 +38,86 @@
#define RENESAS_SDHI_MAX_TAP 3
static unsigned int renesas_sdhi_init_tuning(struct matsu_sd_priv *priv)
static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
{
u32 reg;
/* Initialize SCC */
matsu_sd_writel(priv, 0, MATSU_SD_INFO1);
tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
reg = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
reg &= ~MATSU_SD_CLKCTL_SCLKEN;
matsu_sd_writel(priv, reg, MATSU_SD_CLKCTL);
reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
reg &= ~TMIO_SD_CLKCTL_SCLKEN;
tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
/* Set sampling clock selection range */
matsu_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
tmio_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
RENESAS_SDHI_SCC_DTCNTL);
reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL);
reg |= RENESAS_SDHI_SCC_DTCNTL_TAPEN;
matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL);
reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
matsu_sd_writel(priv, 0x300 /* scc_tappos */,
tmio_sd_writel(priv, 0x300 /* scc_tappos */,
RENESAS_SDHI_SCC_DT2FF);
reg = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
reg |= MATSU_SD_CLKCTL_SCLKEN;
matsu_sd_writel(priv, reg, MATSU_SD_CLKCTL);
reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
reg |= TMIO_SD_CLKCTL_SCLKEN;
tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
/* Read TAPNUM */
return (matsu_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
}
static void renesas_sdhi_reset_tuning(struct matsu_sd_priv *priv)
static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
{
u32 reg;
/* Reset SCC */
reg = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
reg &= ~MATSU_SD_CLKCTL_SCLKEN;
matsu_sd_writel(priv, reg, MATSU_SD_CLKCTL);
reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
reg &= ~TMIO_SD_CLKCTL_SCLKEN;
tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
reg = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
reg |= MATSU_SD_CLKCTL_SCLKEN;
matsu_sd_writel(priv, reg, MATSU_SD_CLKCTL);
reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
reg |= TMIO_SD_CLKCTL_SCLKEN;
tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
}
static void renesas_sdhi_prepare_tuning(struct matsu_sd_priv *priv,
static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
unsigned long tap)
{
/* Set sampling clock position */
matsu_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
}
static unsigned int renesas_sdhi_compare_scc_data(struct matsu_sd_priv *priv)
static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
{
/* Get comparison of sampling data */
return matsu_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
}
static int renesas_sdhi_select_tuning(struct matsu_sd_priv *priv,
static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
unsigned int tap_num, unsigned int taps,
unsigned int smpcmp)
{
......@@ -132,7 +132,7 @@ static int renesas_sdhi_select_tuning(struct matsu_sd_priv *priv,
u32 reg;
/* Clear SCC_RVSREQ */
matsu_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
/* Merge the results */
for (i = 0; i < tap_num * 2; i++) {
......@@ -211,19 +211,19 @@ static int renesas_sdhi_select_tuning(struct matsu_sd_priv *priv,
return -EIO;
/* Set SCC */
matsu_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET);
tmio_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET);
/* Enable auto re-tuning */
reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
return 0;
}
int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
{
struct matsu_sd_priv *priv = dev_get_priv(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = upriv->mmc;
unsigned int tap_num;
......@@ -232,7 +232,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
u32 caps;
/* Only supported on Renesas RCar */
if (!(priv->caps & MATSU_SD_CAP_RCAR_UHS))
if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
return -EINVAL;
/* clock tuning is not needed for upto 52MHz */
......@@ -258,7 +258,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
/* Force PIO for the tuning */
caps = priv->caps;
priv->caps &= ~MATSU_SD_CAP_DMA_INTERNAL;
priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
ret = mmc_send_tuning(mmc, opcode, NULL);
......@@ -288,12 +288,12 @@ out:
static int renesas_sdhi_set_ios(struct udevice *dev)
{
int ret = matsu_sd_set_ios(dev);
int ret = tmio_sd_set_ios(dev);
mdelay(10);
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
struct matsu_sd_priv *priv = dev_get_priv(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
renesas_sdhi_reset_tuning(priv);
#endif
......@@ -302,17 +302,17 @@ static int renesas_sdhi_set_ios(struct udevice *dev)
}
static const struct dm_mmc_ops renesas_sdhi_ops = {
.send_cmd = matsu_sd_send_cmd,
.send_cmd = tmio_sd_send_cmd,
.set_ios = renesas_sdhi_set_ios,
.get_cd = matsu_sd_get_cd,
.get_cd = tmio_sd_get_cd,
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
.execute_tuning = renesas_sdhi_execute_tuning,
#endif
};
#define RENESAS_GEN2_QUIRKS MATSU_SD_CAP_RCAR_GEN2
#define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
#define RENESAS_GEN3_QUIRKS \
MATSU_SD_CAP_64BIT | MATSU_SD_CAP_RCAR_GEN3 | MATSU_SD_CAP_RCAR_UHS
TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
static const struct udevice_id renesas_sdhi_match[] = {
{ .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
......@@ -345,10 +345,10 @@ static int renesas_sdhi_probe(struct udevice *dev)
}
if (fdt_resource_size(&reg_res) == 0x100)
quirks |= MATSU_SD_CAP_16BIT;
quirks |= TMIO_SD_CAP_16BIT;
}
ret = matsu_sd_probe(dev, quirks);
ret = tmio_sd_probe(dev, quirks);
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
if (!ret)
renesas_sdhi_reset_tuning(dev_get_priv(dev));
......@@ -360,9 +360,9 @@ U_BOOT_DRIVER(renesas_sdhi) = {
.name = "renesas-sdhi",
.id = UCLASS_MMC,
.of_match = renesas_sdhi_match,
.bind = matsu_sd_bind,
.bind = tmio_sd_bind,
.probe = renesas_sdhi_probe,
.priv_auto_alloc_size = sizeof(struct matsu_sd_priv),
.platdata_auto_alloc_size = sizeof(struct matsu_sd_plat),
.priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
.platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
.ops = &renesas_sdhi_ops,
};
drivers/mmc/tmio-common.h 0 → 100644
浏览文件 @ cb0b6b03
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __TMIO_COMMON_H__
#define __TMIO_COMMON_H__
#define TMIO_SD_CMD 0x000 /* command */
#define TMIO_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
#define TMIO_SD_CMD_MULTI BIT(13) /* multiple block transfer */
#define TMIO_SD_CMD_RD BIT(12) /* 1: read, 0: write */
#define TMIO_SD_CMD_DATA BIT(11) /* data transfer */
#define TMIO_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
#define TMIO_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */
#define TMIO_SD_CMD_RSP_NONE (3 << 8)/* response: none */
#define TMIO_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */
#define TMIO_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */
#define TMIO_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */
#define TMIO_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */
#define TMIO_SD_ARG 0x008 /* command argument */
#define TMIO_SD_STOP 0x010 /* stop action control */
#define TMIO_SD_STOP_SEC BIT(8) /* use sector count */
#define TMIO_SD_STOP_STP BIT(0) /* issue CMD12 */
#define TMIO_SD_SECCNT 0x014 /* sector counter */
#define TMIO_SD_RSP10 0x018 /* response[39:8] */
#define TMIO_SD_RSP32 0x020 /* response[71:40] */
#define TMIO_SD_RSP54 0x028 /* response[103:72] */
#define TMIO_SD_RSP76 0x030 /* response[127:104] */
#define TMIO_SD_INFO1 0x038 /* IRQ status 1 */
#define TMIO_SD_INFO1_CD BIT(5) /* state of card detect */
#define TMIO_SD_INFO1_INSERT BIT(4) /* card inserted */
#define TMIO_SD_INFO1_REMOVE BIT(3) /* card removed */
#define TMIO_SD_INFO1_CMP BIT(2) /* data complete */
#define TMIO_SD_INFO1_RSP BIT(0) /* response complete */
#define TMIO_SD_INFO2 0x03c /* IRQ status 2 */
#define TMIO_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */
#define TMIO_SD_INFO2_CBSY BIT(14) /* command busy */
#define TMIO_SD_INFO2_SCLKDIVEN BIT(13) /* command setting reg ena */
#define TMIO_SD_INFO2_BWE BIT(9) /* write buffer ready */
#define TMIO_SD_INFO2_BRE BIT(8) /* read buffer ready */
#define TMIO_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */
#define TMIO_SD_INFO2_ERR_RTO BIT(6) /* response time out */
#define TMIO_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */
#define TMIO_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */
#define TMIO_SD_INFO2_ERR_TO BIT(3) /* time out error */
#define TMIO_SD_INFO2_ERR_END BIT(2) /* END bit error */
#define TMIO_SD_INFO2_ERR_CRC BIT(1) /* CRC error */
#define TMIO_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */
#define TMIO_SD_INFO1_MASK 0x040
#define TMIO_SD_INFO2_MASK 0x044
#define TMIO_SD_CLKCTL 0x048 /* clock divisor */
#define TMIO_SD_CLKCTL_DIV_MASK 0x104ff
#define TMIO_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
#define TMIO_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
#define TMIO_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
#define TMIO_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
#define TMIO_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
#define TMIO_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
#define TMIO_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
#define TMIO_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
#define TMIO_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
#define TMIO_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
#define TMIO_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
#define TMIO_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */
#define TMIO_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
#define TMIO_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
#define TMIO_SD_SIZE 0x04c /* block size */
#define TMIO_SD_OPTION 0x050
#define TMIO_SD_OPTION_WIDTH_MASK (5 << 13)
#define TMIO_SD_OPTION_WIDTH_1 (4 << 13)
#define TMIO_SD_OPTION_WIDTH_4 (0 << 13)
#define TMIO_SD_OPTION_WIDTH_8 (1 << 13)
#define TMIO_SD_BUF 0x060 /* read/write buffer */
#define TMIO_SD_EXTMODE 0x1b0
#define TMIO_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
#define TMIO_SD_SOFT_RST 0x1c0
#define TMIO_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */
#define TMIO_SD_VERSION 0x1c4 /* version register */
#define TMIO_SD_VERSION_IP 0xff /* IP version */
#define TMIO_SD_HOST_MODE 0x1c8
#define TMIO_SD_IF_MODE 0x1cc
#define TMIO_SD_IF_MODE_DDR BIT(0) /* DDR mode */
#define TMIO_SD_VOLT 0x1e4 /* voltage switch */
#define TMIO_SD_VOLT_MASK (3 << 0)
#define TMIO_SD_VOLT_OFF (0 << 0)
#define TMIO_SD_VOLT_330 (1 << 0)/* 3.3V signal */
#define TMIO_SD_VOLT_180 (2 << 0)/* 1.8V signal */
#define TMIO_SD_DMA_MODE 0x410
#define TMIO_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
#define TMIO_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
#define TMIO_SD_DMA_CTL 0x414
#define TMIO_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
#define TMIO_SD_DMA_RST 0x418
#define TMIO_SD_DMA_RST_RD BIT(9)
#define TMIO_SD_DMA_RST_WR BIT(8)
#define TMIO_SD_DMA_INFO1 0x420
#define TMIO_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete (uniphier) */
#define TMIO_SD_DMA_INFO1_END_RD BIT(17) /* DMA from device is complete (renesas) */
#define TMIO_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
#define TMIO_SD_DMA_INFO1_MASK 0x424
#define TMIO_SD_DMA_INFO2 0x428
#define TMIO_SD_DMA_INFO2_ERR_RD BIT(17)
#define TMIO_SD_DMA_INFO2_ERR_WR BIT(16)
#define TMIO_SD_DMA_INFO2_MASK 0x42c
#define TMIO_SD_DMA_ADDR_L 0x440
#define TMIO_SD_DMA_ADDR_H 0x444
/* alignment required by the DMA engine of this controller */
#define TMIO_SD_DMA_MINALIGN 0x10
struct tmio_sd_plat {
struct mmc_config cfg;
struct mmc mmc;
};
struct tmio_sd_priv {
void __iomem *regbase;
unsigned long mclk;
unsigned int version;
u32 caps;
#define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
#define TMIO_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
#define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
#define TMIO_SD_CAP_64BIT BIT(3) /* Controller is 64bit */
#define TMIO_SD_CAP_16BIT BIT(4) /* Controller is 16bit */
#define TMIO_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas RCar version of IP */
#define TMIO_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas RCar version of IP */
#define TMIO_SD_CAP_RCAR_UHS BIT(7) /* Renesas RCar UHS/SDR modes */
#define TMIO_SD_CAP_RCAR \
(TMIO_SD_CAP_RCAR_GEN2 | TMIO_SD_CAP_RCAR_GEN3)
#ifdef CONFIG_DM_REGULATOR
struct udevice *vqmmc_dev;
#endif
};
int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data);
int tmio_sd_set_ios(struct udevice *dev);
int tmio_sd_get_cd(struct udevice *dev);
int tmio_sd_bind(struct udevice *dev);
int tmio_sd_probe(struct udevice *dev, u32 quirks);
u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg);
void tmio_sd_writel(struct tmio_sd_priv *priv,
u32 val, unsigned int reg);
#endif /* __TMIO_COMMON_H__ */
drivers/mmc/uniphier-sd.c
浏览文件 @ cb0b6b03
......@@ -17,12 +17,12 @@
#include <power/regulator.h>
#include <asm/unaligned.h>
#include "matsushita-common.h"
#include "tmio-common.h"
static const struct dm_mmc_ops uniphier_sd_ops = {
.send_cmd = matsu_sd_send_cmd,
.set_ios = matsu_sd_set_ios,
.get_cd = matsu_sd_get_cd,
.send_cmd = tmio_sd_send_cmd,
.set_ios = tmio_sd_set_ios,
.get_cd = tmio_sd_get_cd,
};
static const struct udevice_id uniphier_sd_match[] = {
......@@ -32,16 +32,16 @@ static const struct udevice_id uniphier_sd_match[] = {
static int uniphier_sd_probe(struct udevice *dev)
{
return matsu_sd_probe(dev, 0);
return tmio_sd_probe(dev, 0);
}
U_BOOT_DRIVER(uniphier_mmc) = {
.name = "uniphier-mmc",
.id = UCLASS_MMC,
.of_match = uniphier_sd_match,
.bind = matsu_sd_bind,
.bind = tmio_sd_bind,
.probe = uniphier_sd_probe,
.priv_auto_alloc_size = sizeof(struct matsu_sd_priv),
.platdata_auto_alloc_size = sizeof(struct matsu_sd_plat),
.priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
.platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
.ops = &uniphier_sd_ops,
};
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