- 13 1月, 2010 3 次提交
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由 Bryan Wu 提交于
For MUSB devices that do not support multipoint (hubs), we have to emulate a root hub so that we can support core operations like resetting ports. Signed-off-by: NBryan Wu <bryan.wu@analog.com> Signed-off-by: NCliff Cai <cliff.cai@analog.com> Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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- 09 1月, 2010 13 次提交
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由 Chris Zhang 提交于
Adds required definitions for EHCI support in sequoia configuration file. But still keeps the OHCI as default driver. Signed-off-by: NChris Zhang <chris@seamicro.com>
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由 Chris Zhang 提交于
Currently ppc440epx uses OHCI for USB full-speed support. This change adds support for EHCI. Signed-off-by: NChris Zhang <chris@seamicro.com>
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由 Chris Zhang 提交于
In USB ehci driver, the port reset is not terminated. EHCI spec says "A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds". Without termination, a port stays at reset state. This is observed on ppc4xx(sequoia) boards. Signed-off-by: NChris Zhang <chris@seamicro.com>
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由 Sanjeev Premi 提交于
This patch fixes this warning during compile: omap3.c: In function 'musb_platform_init': omap3.c:126: warning: label 'end' defined but not used Problem reported by: Dirk Behme[dirk.behme@googlemail.com] Signed-off-by: NSanjeev Premi <premi@ti.com>
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由 Bryan Wu 提交于
Signed-off-by: NBryan Wu <bryan.wu@analog.com> Signed-off-by: NCliff Cai <cliff.cai@analog.com> Signed-off-by: NMike Frysinger <vapier@gentoo.org> Signed-off-by: NRemy Bohmer <linux@bohmer.net>
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由 Bryan Wu 提交于
The RX Control/Status register has bits that we want to preserve, so don't just write out a single bit. Preserve the others bits in the process. The original code posted to the u-boot list had this behavior, but looks like it was lost somewhere along the way to merging. Signed-off-by: NBryan Wu <bryan.wu@analog.com> Signed-off-by: NCliff Cai <cliff.cai@analog.com> Signed-off-by: NMike Frysinger <vapier@gentoo.org> Signed-off-by: NRemy Bohmer <linux@bohmer.net>
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由 Bryan Wu 提交于
The multipoint handling under MUSB is optional, and some parts (like the Blackfin processor) do not implement support for it. Signed-off-by: NBryan Wu <bryan.wu@analog.com> Signed-off-by: NCliff Cai <cliff.cai@analog.com> Signed-off-by: NMike Frysinger <vapier@gentoo.org> Signed-off-by: NRemy Bohmer <linux@bohmer.net>
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由 Bryan Wu 提交于
The dynamic FIFO handling under MUSB is optional, and some parts (like the Blackfin processor) do not implement support for it. Due to this, the FIFO reading/writing steps need special handling, so mark the common versions weak so drivers can override. Signed-off-by: NBryan Wu <bryan.wu@analog.com> Signed-off-by: NCliff Cai <cliff.cai@analog.com> Signed-off-by: NMike Frysinger <vapier@gentoo.org> Signed-off-by: NRemy Bohmer <linux@bohmer.net>
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由 Mike Frysinger 提交于
Signed-off-by: NMike Frysinger <vapier@gentoo.org> Signed-off-by: NRemy Bohmer <linux@bohmer.net>
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由 Ajay Kumar Gupta 提交于
Adding USB configuration. Default is set for USB MSC host. Signed-off-by: NAjay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: NSwaminathan S <swami.iyer@ti.com>
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由 Ajay Kumar Gupta 提交于
Tested USB host functionality on DA830 EVM. Signed-off-by: NAjay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: NSwaminathan S <swami.iyer@ti.com>
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由 Ajay Kumar Gupta 提交于
Added DA8xx GPIO base addresses in gpio_defs.h and pointers to different BANKs which can be used to program GPIOs. Signed-off-by: NAjay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: NSwaminathan S <swami.iyer@ti.com>
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由 Ajay Kumar Gupta 提交于
USB0_DRVVBUS pinmux configuration is required for USB functinality in uboot. Signed-off-by: NAjay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: NSwaminathan S <swami.iyer@ti.com>
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- 08 1月, 2010 5 次提交
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由 Heiko Schocher 提交于
Add support to configure bus parking mode and master in bus arbitration configuration (ACR). Add this for the kmeter1 port: Configure bus arbiter with recommended values from Freescale to improve bus latency/throughput for application with intensive QuiccEngine activity. Signed-off-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Reinhard Arlt 提交于
Remove PCI reset, if there is a monarch PMC module. Signed-off-by: NReinhard Arlt <reinhard.arlt@esd.eu> Signed-off-by: NStefan Roese <sr@denx.de> convert clrbits_be32 + setbits_be32 to clrsetbits_be32, use out_be32 to set gcr. Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Reinhard Arlt 提交于
The caddy2 is a variant of the already supported vme8349. So we just add the differences to this board port. To better support those two boards we switched from fixed SDRAM configuration to usage of spd_sdram(). This is done by providing a board specific SPD EEPROM routine with different values for both boards. Signed-off-by: NReinhard Arlt <reinhard.arlt@esd.eu> Signed-off-by: NStefan Roese <sr@denx.de> changed to use mkconfig -t option instead, plus misc codingstyle fixes. Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Stefan Roese 提交于
The memory controller could already be enabled, when spd_sdram() is called. This could be the case for example, when the SDRAM is initialized by the JTAG debugger. The "sync" after the register access via the accessor function is still needed, because the macro uses the sync before the real write is done. So until not all accesses are converted to using accessor functions, this sync still needs to be made "manually" here. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd.eu> Acked-by: NDave Liu <daveliu@freescale.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Anton Vorontsov 提交于
The core support for NAND booting is there already, so this patch is pretty straightforward. There is one trick though: top level Makefile expects nand_spl to be in nand_spl/board/$(BOARDDIR), but we can fully reuse the code from mpc8313erdb boards, and so to not duplicate the code we just symlink nand_spl/board/freescale/mpc8315erdb to mpc8313erdb. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> o silence make during ln echo o update documentation o and avoid: $ ./MAKEALL MPC8315ERDB_NAND Configuring for MPC8315ERDB board... sdram.o: In function `fixed_sdram': /home/r1aaha/git/u-boot/nand_spl/board/freescale/mpc8313erdb/sdram.c:72: undefined reference to `udelay' by renaming udelay -> __udelay in the spirit of commit 3eb90bad "Generic udelay() with watchdog support". Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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- 06 1月, 2010 19 次提交
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由 Becky Bruce 提交于
Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Dave Liu 提交于
In chip-select interleaving case, we also need set the ODT_RD_CFG and ODT_WR_CFG in cs1_config register. Signed-off-by: NDave Liu <daveliu@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Dave Liu 提交于
Different boards may require different settings of Dynamic ODT (Rtt_Wr). We provide a means to allow the board specific code to provide its own value of Rtt_Wr. Signed-off-by: NDave Liu <daveliu@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Dave Liu 提交于
add the override for write leveling sampling and start time according to specific board. Signed-off-by: NDave Liu <daveliu@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Dave Liu 提交于
1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but It should be set to tXP parameter, tXP=max(3CK, 7.5ns) 2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter We are setting the mode register MR0[A12]='1' Signed-off-by: NDave Liu <daveliu@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Anton Vorontsov 提交于
Thanks to "Errata to MPC8569E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 0" document, which describes all eSDHC pins, we can add 4-bits eSDHC support for MPC8569E-MDS boards. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
We incorrectly had the sense of PME_CLK_SEL, FM1_CLK_SEL, FM2_CLK_SEL backwards so we report the wrong frequency. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Li Yang 提交于
Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
We already map the page cache-inhibited. There is no reason we shouldn't also be marking it guarded to prevent speculative accesses. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Various SoC errata are specific to a given revision of silicon. This patch gives us a simple macro to use when doing such tests. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Dave Liu 提交于
We need to add the readback to bootpage translation LAW to make it effect. Signed-off-by: NDave Liu <daveliu@freescale.com> Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Rather than hard coding which TLB entry the FLASH is mapped with we can use find_tlb_idx to determine the entry. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Now that we dynamically determine TLB CAM entries to use we dont need CONFIG_SYS_DDR_TLB_START anymore. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Now that we track which TLB CAM entries are used we can allocate entries on the fly. Change the SPD DDR TLB setup code to assume we use at most 8 TLBs (or the number free, which ever is fewer). Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
We need to track which TLB CAM entries are used to allow us to "dynamically" allocate entries later in the code. For example the SPD DDR code today hard codes which TLB entries it uses. We can now make that pick entries that are free. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent that uses the standard PCI programming model to determine host vs agent/end-point. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
We can use fsl_setup_hose to determine if we are a agent/end-point or a host. Rather than using some SoC specific register we can just look at the PCI cfg space of the host controller to determine this. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
We can use fsl_setup_hose to determine if we are a agent/end-point or a host. Rather than using some SoC specific register we can just look at the PCI cfg space of the host controller to determine this. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
We can use fsl_setup_hose to determine if we are a agent/end-point or a host. Rather than using some SoC specific register we can just look at the PCI cfg space of the host controller to determine this. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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