- 23 11月, 2014 1 次提交
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由 Masahiro Yamada 提交于
Since commit 0defddc8 (config: Add a default CONFIG_SYS_PROMPT), each board header does not need to define CONFIG_SYS_PROMPT as long as it uses the default prompt "=> ". Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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- 17 10月, 2014 2 次提交
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由 Ruchika Gupta 提交于
Enable blob commands for platforms having SEC 4.0 or greater for secure boot scenarios Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ruchika Gupta 提交于
Enable CAAM in platforms supporting the hardware block. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 31 7月, 2014 1 次提交
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由 Masahiro Yamada 提交于
Now CONFIG_SPL and CONFIG_TPL are defined in Kconfig. Remove the redundant definition in config headers. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 30 7月, 2014 1 次提交
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由 Masahiro Yamada 提交于
We are about to switch to Kconfig in the next commit. But there are something to get done beforehand. In Kconfig, include/generated/autoconf.h defines boolean CONFIG macros as 1. CONFIG_SPL and CONFIG_TPL, if defined, must be set to 1. Otherwise, when switching to Kconfig, the build log would be sprinkled with warning messages like this: warning: "CONFIG_SPL" redefined [enabled by default] Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 24 7月, 2014 1 次提交
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由 Shengzhou Liu 提交于
Tested with NOR boot and NAND boot on T2080QDS and T2080RDB. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
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- 23 7月, 2014 1 次提交
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由 Shengzhou Liu 提交于
Remove unnecessary condition CONFIG_RAMBOOT_PBL to have SST and EON SPI flash work in case of NOR boot. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 06 6月, 2014 1 次提交
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由 Shengzhou Liu 提交于
- add support for 2nd DIMM slot. - make it work with DIMM which is less than 2GB. Verified with two 2GB UDIMM MT9JSF25672AZ-2G1K1 in two DIMM slots. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 17 5月, 2014 2 次提交
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由 Liu Gang 提交于
The new 768KB u-boot image size requires changes for SRIO/PCIE boot. These addresses need to be updated to appropriate locations. The updated addresses are used to configure the SRIO/PCIE inbound windows for the boot, and they must be aligned with the window size based on the SRIO/PCIE modules requirement. So for the 768KB u-boot image, the inbound window cannot be set with 0xfff40000 base address and 0xc0000 size, it should be extended to 1MB size and the base address can be aligned with the size. Signed-off-by: NLiu Gang <Gang.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Kim Phillips 提交于
AFAICT, c=ffe does nothing and was a typo from the original commit d1712369 "powerpc/p4080: Add support for the P4080DS board" and just kept on getting duplicated in subsequently added board config files. Signed-off-by: NKim Phillips <kim.phillips@freescale.com> Acked-by: NEdward Swarthout <ed.swarthout@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 23 4月, 2014 5 次提交
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由 Shengzhou Liu 提交于
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(160K) to it, SPL further initializes DDR using SPD and environment and copy u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix boards.cfg for T2081QDS_SDCARD and _SPIFLASH] Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
U-boot binary size has been increased from 512KB to 768KB. So update CONFIG_SYS_MONITOR_LEN to reflect the same. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
We use dynamical mtdparts partition instead of directly puting mtd partitions nodes in device tree. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
NOR flash is on CS1 instead of CS2 when NAND boot. So correct NOR chip selection to CS1 from CS2. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Zhao Qiang 提交于
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: NZhao Qiang <B45475@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 13 3月, 2014 1 次提交
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由 Masahiro Yamada 提交于
Pull out "$(SRCTREE)/" from CONFIG_SYS_FSL_PBL_PBI and CONFIG_SYS_FSL_PBL_RCW and push it into the top Makefile. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: York Sun <yorksun@freescale.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
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- 08 3月, 2014 1 次提交
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由 Shengzhou Liu 提交于
Change QIXIS timing parameter CONFIG_SYS_CS3_FTIM2 to 8 from 0. Fix EMI2 for t2080qds, which was caused by adding t2081qds. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 25 2月, 2014 1 次提交
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由 Shengzhou Liu 提交于
T2081 QDS is a high-performance computing evaluation, development and test platform supporting the T2081 QorIQ Power Architecture processor. T2081QDS board Overview ----------------------- - T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz - 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC) - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving - Ethernet interfaces: - Two on-board 10M/100M/1G bps RGMII ports - Two 10Gbps XFI with on-board SFP+ cage - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card - Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC - SerDes: - 8 lanes up to 10.3125GHz - Supports SGMII, HiGig, XFI, XAUI and Aurora debug, - IFC: - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA - eSPI: - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) - USB: - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB) - PCIe: - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - eSDHC: - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and voltage translators - I2C: - Four I2C controllers. - UART: - Dual 4-pins UART serial ports Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 19 2月, 2014 1 次提交
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由 Masahiro Yamada 提交于
This commit removes platform CONFIG_SYS_HZ definition for the remainders of part1 (commit cdb23792) and part2 (commit f232950f). Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Rob Herring <rob.herring@calxeda.com>
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- 25 1月, 2014 1 次提交
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由 Masahiro Yamada 提交于
Define CONFIG_MPC85xx in arch/powerpc/cpu/mpc85xx/config.mk because all target boards with mpc85xx cpu define it. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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- 22 1月, 2014 2 次提交
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由 Prabhakar Kushwaha 提交于
u-boot binary size for Freescale mpc85xx platforms is 512KB. This has been reached to upper limit for some of the platforms causig linker error. So, Increase the u-boot binary size to 768KB. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
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由 Prabhakar Kushwaha 提交于
Rename CONFIG_PBLRCW_CONFIG and CONFIG_PBLRCW_CONFIG. Also add their details in README. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 05 12月, 2013 1 次提交
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由 Shengzhou Liu 提交于
Usually CONFIG_FSL_DDR_INTERACTIVE feature is used for debug. we would not enable this by default to save the limited space of u-boot. This avoid following compiling error: section .bootpg loaded at [00000000effff000,00000000effff577] overlap ssection .data loaded at [00000000efff31b8,00000000f00010c7] u-boot: section .bootpg lma 0xeffff000 adjusted to 0xf00010c8 Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: NYork Sun <yorksun@freescale.com>
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- 26 11月, 2013 3 次提交
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由 Shengzhou Liu 提交于
Add the default RCW(SerDes 0x66_0x16) and PBI configure file for T2080QDS board, so we can use PBL tool to generate the ramboot image to support boot from NAND/SPI/SD. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
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由 Shengzhou Liu 提交于
The T2080QDS is a high-performance computing evaluation, development and test platform supporting the T2080 QorIQ Power Architecture processor. T2080QDS feature overview Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz Memory: - Single memory controller capable of supporting DDR3 and DDR3-LV devices - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support Ethernet interfaces: - Two 1Gbps RGMII on-board ports - Four 10Gbps XFI on-board cages - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes: - 16 lanes up to 10.3125GHz - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI IFC: - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA eSPI: - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) USB: - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB) PCIE: - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) SATA: - Two SATA 2.0 ports on-board SRIO: - Two Serial RapidIO 2.0 ports up to 5 GHz eSDHC: - Supports SD/SDHC/SDXC/eMMC Card I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports System Logic: - QIXIS-II FPGA system controll Debug Features: - Support Legacy, COP/JTAG, Aurora, Event and EVT Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: removed Makefile blank line at EOF, fix conflicts with moving DDR driver] Acked-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: NYork Sun <yorksun@freescale.com>
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- 05 11月, 2013 2 次提交
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由 Rob Herring 提交于
Remove platform CONFIG_SYS_HZ definition for configs A-Z*. Signed-off-by: NRob Herring <rob.herring@calxeda.com>
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由 Rob Herring 提交于
The definitions for CONFIG_SYS_PROMPT are varied with little reason other than to display the board name. Over half the definitions are "==> ", so make this the default. The rest of the boards remain unchanged to avoid breaking any external scripts expecting a certain prompt. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com>
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- 17 10月, 2013 2 次提交
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由 Shaohui Xie 提交于
Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a pbl boot image. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
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由 Po Liu 提交于
This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: NPo Liu <Po.Liu@freescale.com>
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- 10 8月, 2013 3 次提交
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由 Minghuan Lian 提交于
1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860. 2. Decrease RMan liodn offset number. SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3. For t4240 and b4860, RMan liodn base is assigned to 922, the original offset number is too large that the liodn (base+offset 922+678 = 1600) is greater than 0x500 the maximum liodn number. Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 Shaveta Leekha 提交于
1) Add support in B4860 board files for using IDT driver where IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer that generate different refclks for SerDes modules, used this driver for reconfiguring SerDes1 Refclks(based on SerDes1 protocols) for CPRI to work. CPRI works on 122.88MHz and default refclks coming on board are not suitable for it 2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file to b4860qds board file, as SerDes1 Refclk1 would come from PHY MUX in case of certain protocols, that have been checked here. This change would make on board SGMIIs to work 3) Add I2C addresses for IDT8T49N222A devices in board/include file 4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist Signed-off-by: NShaveta Leekha <shaveta@freescale.com> Acked-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board specific feature and belongs to SoC header. Signed-off-by: NYork Sun <yorksun@freescale.com>
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- 24 7月, 2013 1 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: NTom Rini <trini@ti.com>
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- 23 7月, 2013 1 次提交
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由 Heiko Schocher 提交于
- added to fsl_i2c driver new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: NHeiko Schocher <hs@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@wwwdotorg.org>
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- 21 6月, 2013 3 次提交
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由 Prabhakar Kushwaha 提交于
Relax parameters to give address latching more time to setup. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Liu Gang 提交于
When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: NLiu Gang <Gang.Liu@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Liu Gang 提交于
B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro "CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature when building the u-boot image. You can get some description about this macro in README file, and for more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: NLiu Gang <Gang.Liu@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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- 08 6月, 2013 1 次提交
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由 Gabor Juhos 提交于
The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
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- 25 5月, 2013 1 次提交
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由 Shaveta Leekha 提交于
Signed-off-by: NShaveta Leekha <shaveta@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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