To reset the DM after a new dtb is loaded, we need to call dm_uninit()
and then dm_init(). This fails however because gd->dm_root is not nullified
by dm_uninit().
Fixing it by setting gd->dm_root in dm_uninit().
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NHeiko Schocher <hs@denx.de>

It is currently not possible to include the support to remove devices in
the SPL. This is however needed by platforms that re-select their dtb after
DM is initialized; they need to remove all the previously bound devices
before triggering a scan of the new DT.

Add a Kconfig option to be able to include the support for device removal
in the SPL.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Seeries-changes:3
- update commit message
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

In some cases it may be useful to be able to change the fdt we have been
using and use another one instead. For example, the TI platforms uses an
EEPROM to store board information and, based on the type of board,
different dtbs are used by the SPL. When DM_I2C is used, a first dtb must
be used before the I2C is initialized and only then the final dtb can be
selected.
To speed up the process and reduce memory usage, introduce a new function
fdtdec_setup_best_match() that re-use the DTBs loaded in memory by
fdtdec_setup() to select the best match.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

This is required to take advantage of MULTI_DTB_FIT before relocation.
If it is too low, DM will be initialized only after relocation has
taken place. That is too late for the DRA7 because I2C DM is used before
the relocation to setup the voltages required, among other things, to
properly initialize the DRAM.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

am57xx configs uses DM_I2C both in SPL and u-boot.
Remove code for non-DM I2C support.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C
API when DM_I2C is used. The goal is to eventually remove DM_I2C_COMPAT
when all I2C "clients" have been migrated to use the DM API.
This a step in that direction for the TI based platforms.
Build tested with buildman:
buildman -dle am33xx ti omap3 omap4 omap5 davinci keystone

boot tested with:
am335x_evm, am335x_boneblack, am335x_boneblack_vboot (DM version),
am57xx_evm, dra7xx_evm, k2g_evm, am437x_evm
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Remove the last call to the non-DM I2C API.
Also remove the #undef CONFIG_DM_I2C_COMPAT because it is not defined
in the common header file anymore.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NFelix Brack <fb@ltec.ch>
Tested-by: NFelix Brack <fb@ltec.ch>
Reviewed-by: NHeiko Schocher <hs@denx.de>

The EEPROM reading in the board detection code is done through legacy
I2C functions which on platforms using DM_I2C this functionality is
provided via the CONFIG_DM_I2C_COMPAT layer. To allow newer platforms
to use the board detection code without relying on CONFIG_DM_I2C_COMPAT
go ahead and add an I2C handling implementation that directly uses the
I2C DM functionality.
Signed-off-by: NAndreas Dannenberg <dannenberg@ti.com>
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Those driver are not DM drivers per se (not using the PMIC/regulator
framework) and are using the legacy I2C API. Make them compatible with
the DM_I2C API.

This impacts the following drivers:
- palmas (used by am57xx/dra7xx evms)
- tps65218 (used by am43xx evms)
- tps65217 and tps65910 (used by am335x evms and am335x boneblack vboot)
- twl4030 (used by omap3_logicpd)
- tps65217 (used by brppt1)
- twl6030
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

In order to use DM_I2C, we need to move the board detection after the
early SPL initialization.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

If DM_I2C is used , the I2C controllers must be registered as U_BOOT_DEVICE
because OF_CONTROL is not used in the SPL.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

This allows the driver to be used without OF_CONTROL.
AM335x support DM_SPL but does not use SPL_OF_CONTROL. Enabling DM_I2C in
SPL thus requires that the omap I2C can be passed platdata.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Move away from SoC specific headers to handle different register layout.
Instead use driver data to get appropriate register layouts like in the
kernel. While at it, perform some mostly cosmetic alignment/cleanup in
the functions being updated.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Signed-off-by: NAndreas Dannenberg <dannenberg@ti.com>
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Those platforms need CONFIG_SPL_DM_SEQ_ALIAS because they enable both
DM_I2C and SPL_DM. Without CONFIG_SPL_DM_SEQ_ALIAS, it is not possible to
get the I2C bus with i2c_get_chip_for_busnum().
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NFelix Brack <fb@ltec.ch>
Tested-by: NFelix Brack <fb@ltec.ch>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

If OF_CONTROL is not enabled and DM_SEQ_ALIAS is enabled, we must
assign an alias (requested sequence number) to devices that belongs to a
class with the DM_UC_FLAG_SEQ_ALIAS flag. Otherwise
uclass_find_device_by_seq() cannot be used to get/probe a device. In
particular i2c_get_chip_for_busnum() cannot be used.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NHeiko Schocher <hs@denx.de>

i2c_get_chip_for_busnum() really should check the presence of the chip on
the bus. Most of the users of this function assume that this is done.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

The implementation of the EEPROM commands does not support the DM I2C API.
Prevent compilation breakage by not enabling it if the non-DM API is not
available (if DM_I2C is used without DM_I2C_COMPAT)
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

This was unintentionally removed when syncing with upstream.
Signed-off-by: NChris Packham <judge.packham@gmail.com>

- Sync DDR training with Marvell code for Armada 38x by Chris
- Misc updates to Armada 38x Helios4 board by Aditya

The CRC16-CCITT checksum function is useful for space-constrained
applications (such as obtaining a checksum across a 2KBit or 4KBit
EEPROM) in boot applications. It has not been accessible from boot
scripts until now (due to not having a dedicated command and not being
supported by the hash infrstructure) limiting its applicability
outside of custom commands.

This adds the CRC16-CCITT (poly 0x1021, init 0x0) algorithm to the
list of available hashes and adds a new crc16_ccitt_wd_buf() to make
this possible.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
[trini: Fix building crc16.o for SPL/TPL]
Signed-off-by: NTom Rini <trini@konsulko.com>

This merges the CRC16-CCITT headers into u-boot/crc.h to prepare for
rolling CRC16 into the hash infrastructure.  Given that CRC8, CRC32
and CRC32-C already have their prototypes in a single header file, it
seems a good idea to also include CRC16-CCITT in the same.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Similar to Clearfog rev 2.1, GPIO 19 also used to reset onboard ethernet
PHY.

This patch depend on
net: mvneta: Add GPIO configuration support
[URL: https://patchwork.ozlabs.org/patch/1007736/]
Signed-off-by: NAditya Prayoga <aditya@kobol.io>
Reviewed-by: NStefan Roese <sr@denx.de>
Tested-By: NDennis Gilmore <dgilmore@redhat.com>
Reviewed-By: NDennis Gilmore <dgilmore@redhat.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Enable SPI flash support under U-Boot and SPL. The ENV size and offset,
ported from U-Boot 2013.01 Marvell version: 2015_T1.0p16

To create U-Boot image for SPI flash, user would need to replace
* CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC with CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
* CONFIG_ENV_IS_IN_MMC with CONFIG_ENV_IS_IN_SPI_FLASH
Signed-off-by: NAditya Prayoga <aditya@kobol.io>
Reviewed-by: NStefan Roese <sr@denx.de>
Tested-By: NDennis Gilmore <dgilmore@redhat.com>
Reviewed-By: NDennis Gilmore <dgilmore@redhat.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Remove unused I2C support in SPL and use simple_malloc functions to
reduce SPL image size.
Since Helios4 does not have any PCIe allocated on SerDes, remove PCI
support. MTD layer on top of SPI flash is not needed, remove it also.
Signed-off-by: NAditya Prayoga <aditya@kobol.io>
Reviewed-by: NStefan Roese <sr@denx.de>
Tested-By: NDennis Gilmore <dgilmore@redhat.com>
Reviewed-By: NDennis Gilmore <dgilmore@redhat.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Make use of U-Boot's GPIO DM to control native GPIO and I2C IO expander.
Signed-off-by: NAditya Prayoga <aditya@kobol.io>
Reviewed-by: NStefan Roese <sr@denx.de>
Tested-By: NDennis Gilmore <dgilmore@redhat.com>
Reviewed-By: NDennis Gilmore <dgilmore@redhat.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Enable Marvell I2C driver and I2C IO expander. Set default bus to
external I2C bus. Define I2C aliases in device tree so it can be
recognized by the driver.
Signed-off-by: NAditya Prayoga <aditya@kobol.io>
Reviewed-by: NStefan Roese <sr@denx.de>
Tested-By: NDennis Gilmore <dgilmore@redhat.com>
Reviewed-By: NDennis Gilmore <dgilmore@redhat.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Store the environment before 1M into the block device.
This constant is easier to remember, saves a little space,
and is in line with what SolidRun's 2018.01-based fork does for the
clearfog.
Signed-off-by: NJosua Mayer <josua.mayer97@gmail.com>
[ Aditya Prayoga:
* Port forward]
Signed-off-by: NAditya Prayoga <aditya@kobol.io>
Reviewed-by: NStefan Roese <sr@denx.de>
Tested-By: NDennis Gilmore <dgilmore@redhat.com>
Reviewed-By: NDennis Gilmore <dgilmore@redhat.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-18.09 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
Specifically this syncs with commit 99d772547314 ("Bump mv_ddr to
release armada-18.09.2").

The complete log of changes is best obtained from the mv-ddr-marvell.git
repository but some relevant highlights are:

  ddr3: add missing txsdll parameter
  ddr3: fix tfaw timimg parameter
  ddr3: fix trrd timimg parameter
  merge ddr3 topology header file with mv_ddr_topology one
  mv_ddr: a38x: fix zero memory size scrubbing issue

The upstream code is incorporated omitting the portions not relevant to
Armada-38x and DDR3. After that a semi-automated step is used to drop
unused features with unifdef

    find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
        xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
                 -UCONFIG_APN806 -UCONFIG_MC_STATIC \
                 -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
                 -UCONFIG_64BIT -UCONFIG_A3700 -UA3900 -UA80X0 \
                 -UA70X0
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NStefan Roese <sr@denx.de>
Tested-by: NBaruch Siach <baruch@tkos.co.il>
Signed-off-by: NStefan Roese <sr@denx.de>

- Various axp209 fixes
- Fixes for OLinuXino-A20-Lime2 / OLinuXino-A20-Lime2-eMMC

Two fixes for the Amlogic Pinctrl driver :
- bad usage of clrsetbits_le32
- bad pin definition for AXG Family

Now that the Allwinner port in the official mainline ARM Trusted
Firmware repository has reached feature parity with the "legacy" ATF
port, let's use the opportunity to update the Allwinner 64-bit build
instructions. This changes:
- Update ATF build instructions to use the mainline repo.
- Add quick command lines for TL;DR people.
- Mention Allwinner H6 build target.
- Mention pre-built FEL binaries.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

The lime2 features a too large capacitor on the LDO3 output, which
causes the PMIC to shutdown when enabling power. To be able to still
boot up however, we must gradually enable power on LDO3 for this board.

We do this by enabling both the inrush quirk and the maximum slope the
AXP209 supports.
Signed-off-by: NPriit Laes <plaes@plaes.org>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>

The lime2 features a too large capacitor on the LDO3 output, which
causes the PMIC to shutdown when enabling power. To be able to still
boot up however, we must gradually enable power on LDO3 for this board.

We do this by enabling both the inrush quirk and the maximum slope the
AXP209 supports.
Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl>
Signed-off-by: NPriit Laes <plaes@plaes.org>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>

Some boards feature a capacitance on LDO3's output that is too large,
causing inrush currents which as a result, shut down the AXP209. This
has been reported before, without knowing the actual cause.

A fix appeared to be done with
commit 0e6e34ac ("sunxi: Olimex A20 boards: Enable LDO3 and LDO4 regulators").

The description there is a bit misleading, the kernel does not hang
during AXP209 initialization, the PMIC shuts down, causing voltages to
drop and thus the whole system freezes.

While the AXP209 does have the ability to ramp up the voltage slowly, to
reduce these inrush currents, the voltage rate control (VRC) however is
not applicable when switching on the LDO3 output. Only when going from
an enabled lower voltage setting, to a higher voltage setting is the VRC
in effect.

To work around this problem, we set LDO3 to the lowest possible setting
of 0.7 V if it was not yet enabled, and then let the VRC (if enabled) do
its thing. It should be noted, that for some undocumented reason, there
is a short delay needed between setting the LDO3 voltage register and
enabling the power. One would expect that this delay ought to be just
after enabling the output power at 0.7 V, but this did not work.
Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl>
Signed-off-by: NPriit Laes <plaes@plaes.org>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>

The AXP209 LDO3 regulator supports voltage rate control, or can set a
slew rate.

This allows for the power to gradually rise up to the desired voltage,
instead of spiking up as fast as possible. Reason to have this can be
to reduce the inrush currents for example.

There are 3 slopes to choose from, the default, 'none' is a voltage rise
of 0.0167 V/uS, a 1.6 mV/uS and a 0.8 mV/uS voltage rise.

In ideal world (where vendors follow the recommended design guidelines)
this setting should not be enabled by default. Unless of course AXP209
crashes instead of reporting overcurrent condition as it normally should
do in this case.
Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl>
Signed-off-by: NPriit Laes <plaes@plaes.org>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>

The AXP209 has a few 'magisc-ish' values that are better served with
clear defines.
Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl>
Signed-off-by: NPriit Laes <plaes@plaes.org>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>

Use a define for the chip version mask on the axp209.
Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl>
Signed-off-by: NPriit Laes <plaes@plaes.org>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>

Use the standard BIT() macro for bitfield definitions in headers.
Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl>
Signed-off-by: NPriit Laes <plaes@plaes.org>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>

When we clear a pmic_bus bit, we do a read-modify-write operation.
We waste some time however, by writing back the exact samea value
that was already set in the chip. Let us thus only do the write
in case data was changed.
Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl>
Signed-off-by: NPriit Laes <plaes@plaes.org>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>