Move original spl to tpl, and add spl to load next stage firmware,
adapt all the address and option for them.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

TPL stack may different from SPL and sys stack, add support for
separate one when the board defines it.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY
and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

This is fix to:
e2a12f590d rockchip: use 'arch-rockchip' as header file path

The V2 of origin patch set has fix this, but we merge V1 by
mistake, so lets correct it.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

boot0.h and gpio.h will be used by system and include by
'asm/arch/', each of them need of a copy from 'asm/arch-rockchip'.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach,
which is a cheap development platform with RZ/A1H SoC. The
DTs are imported from Linux 5.0.11, commit d5a2675b207d .

Currently supported are UART, ethernet and RPC SPI. The board
can be booted from RPC SPI by writing the u-boot.bin binary
to the beginning of the SPI NOR, e.g. using the "sf" command.
The board can also be booted via JTAG by setting text base to
0x20020000, loading u-boot.bin there via JTAG and executing it
from that address.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC.
Distinguishing feature of this SoC is that it has up to
10 MiB of on-SoC static RAM (SRAM).

The DTs are imported from Linux 5.0.11, commit d5a2675b207d .
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

There are no more boards using this CPU and there is no prospect
of any boards showing up soon, remove it.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>

Last change to this board was done in 2016, it uses non-DM USB
with no prospects of ever being converted to DM USB, drop it.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>

There are no more boards using this CPU and there is no prospect
of any boards showing up soon, remove it.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>

Last change to this board was done in 2016, it uses non-DM USB
with no prospects of ever being converted to DM USB, drop it.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>

Send CONFIG_STATUS and RECONFIG_STATUS mailbox commands to Secure
Device Manager (SDM) to get the status of FPGA and make sure the
FPGA is in user mode before enable the bridge.
Signed-off-by: NAng, Chee Hong <chee.hong.ang@intel.com>

Software must never reset FPGA2SOC bridge. This bridge must only be
reset by POR/COLD/WARM reset. Asserting the FPGA2SOC reset by software
can cause the SoC to lock-up if there are traffics being drived into
FPGA2SOC bridge.
Signed-off-by: NAng, Chee Hong <chee.hong.ang@intel.com>

Convert Stratix 10 SDRAM driver to device model.

Get rid of call to socfpga_per_reset() and use reset
framework.

SPL is changed from calling function in SDRAM driver
directly to just probing UCLASS_RAM.

Move sdram_s10.h from arch to driver/ddr/altera directory.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add SDRAM device tree node.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Compile ALTERA_SDRAM driver in SPL only.
Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

for suspend/resume robustness

update value for ext_phy_ctrl_36 for suspend/resume robustness
with hardware leveling enabled.

Match recommended values from EMIF Tools app note:

http://www.ti.com/lit/an/sprac70/sprac70.pdfSigned-off-by: NBrad Griffis <bgriffis@ti.com>
Signed-off-by: NKeerthy <j-keerthy@ti.com>

In case of RTC+DDR resume, need to restore EMIF context
before initiating hardware leveling.
Signed-off-by: NBrad Griffis <bgriffis@ti.com>
[j-keerthy@ti.com Fixed the am335x build issues]
Signed-off-by: NKeerthy <j-keerthy@ti.com>

Enable HW leveling in RTC+DDR path. The mandate is to enable
HW leveling bit and then wait for 1 ms before accessing any
register.
Signed-off-by: NBrad Griffis <bgriffis@ti.com>
Signed-off-by: NKeerthy <j-keerthy@ti.com>

Add 1ms delay to avoid L3 timeout error during suspend resume.
Signed-off-by: NBrad Griffis <bgriffis@ti.com>
Signed-off-by: NKeerthy <j-keerthy@ti.com>

Adjust DQS skew in case where invert_clkout=1 is used.
Match recommended values from EMIF Tools app note:

http://www.ti.com/lit/an/sprac70/sprac70.pdfSigned-off-by: NBrad Griffis <bgriffis@ti.com>
Signed-off-by: NKeerthy <j-keerthy@ti.com>

This fixes SPL linker script size checks for 3 lds files where the size
checks were implemented as "x < YYY_MAX_SIZE".

Fix the size checks to be "x <= YYY_MAX_SIZE" instead.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Select the PL310 UCLASS_CACHE driver for SoCFPGA.
Reviewed-by: NMarek Vasut <marex@denx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NDinh Nguyen <dinguyen@kernel.org>

Find the UCLASS_CACHE driver to configure the cache controller's
settings.
Reviewed-by: NMarek Vasut <marex@denx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NDinh Nguyen <dinguyen@kernel.org>

Add the PL310 macros for latency control setup, read and write bits.
Reviewed-by: NMarek Vasut <marex@denx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NDinh Nguyen <dinguyen@kernel.org>

On AM654 SoC(arm64) which is IO coherent and has L3 Cache, cache
maintenance operations being done to support non-coherent platforms
causes issues.

For example, here is how U-Boot prepares/handles a buffer to receive
data from a device (DMA Write). This may vary slightly depending on the
driver framework:

	Start DMA to write to destination buffer
	Wait for DMA to be done (dma_receive()/dma_memcpy())
	Invalidate destination buffer (invalidate_dcache_range())
	Read from destination buffer

The invalidate after the DMA is needed in order to read latest data from
memory that’s updated by DMA write. Also, in case random prefetch has
pulled in buffer data during the “wait for DMA” before the DMA has
written to it. This works well for non-coherent architectures.

In case of coherent architecture with L3 cache, DMA write would directly
update L3 cache contents (assuming cacheline is present in L3) without
updating the DDR memory. So invalidate after “wait for DMA” in above
sequence would discard latest data and read will cause stale data to be
fetched from DDR. Therefore invalidate after “wait for DMA” is not
always correct on coherent architecture.

Therefore, provide a Kconfig option to disable cache maintenance ops on
coherent architectures. This has added benefit of improving the
performance of DMA transfers as we no longer need to invalidate/flush
individual cache lines(especially for buffer thats several KBs in size).

In order to facilitate use of same Kconfig across different
architecture, I have added the symbol to top level arch/Kconfig file.
Patch currently disables cache maintenance ops for arm64 only.
flush_dcache_all() and invalidate_dcache_all() are exclusively used
during enabling/disabling dcache and hence are not disabled.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>

To assure the pins on R-Car Gen3 SoCs are configured correctly, always
select pin control drivers on Gen3 SoCs.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

>From way back in 2015:

  commit dffb86e4
  Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  Date:   Wed Aug 12 07:31:54 2015 +0900

    of: flip CONFIG_SPL_DISABLE_OF_CONTROL into CONFIG_SPL_OF_CONTROL

    As we discussed a couple of times, negative CONFIG options make our
    life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ...
    and here is another one.

    Now, there are three boards enabling OF_CONTROL on SPL:
     - socfpga_arria5_defconfig
     - socfpga_cyclone5_defconfig
     - socfpga_socrates_defconfig

    This commit adds CONFIG_SPL_OF_CONTROL for them and deletes
    CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert
    the logic.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The support for DaVinci DM* SoCs has been dropped a while ago. There's
still a lot of leftover code in mach-davinci though. Entirely remove
certain files and modify the common code to no longer reference
unsupported chips.

Note: all DaVinci platforms supported in u-boot now define SOC_DA8XX
but not all define SOC_DA850 (e.g. omapl138). We can safely remove
all ifdefs for the former, but let's leave the ones for the latter.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>

The support for DaVinci DM* boards has been dropped a while ago. The
code for all those PHYs is no longer used and they have their own
proper PHY drivers in drivers/net/phy anyway. Remove all dead code.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>

There are a few functions defined in the header file, but they are
not referenced by any Davinci code.  In order to make a general
function in the future with static function declarations, this
patch will remove the references all together.
Signed-off-by: NAdam Ford <aford173@gmail.com>

Update device tree for luton to add support for luton pcb90.
This pcb has 24 ports from which 12 ports are connected to
SerDes6G.
Signed-off-by: NHoratiu Vultur <horatiu.vultur@microchip.com>

Currently mach-mt7620 contains only support for mt7628. To avoid confusion,
rename mach-mt7620 to mach-mtmips, which means MediaTek MIPS platforms.
MT7620 and MT7628 should be distinguished by SOC_MT7620 and SOC_MT7628
because they do not share the same lowlevel codes.

Dependencies of four drivers are changed to SOC_MT7628 as these drivers
are only used by MT7628.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: NStefan Roese <sr@denx.de>
Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>

Update device tree for ocelot to add support for ocelot pcb120.
Signed-off-by: NHoratiu Vultur <horatiu.vultur@microchip.com>

Update Ocelot network driver to have support also for pcb120.
Signed-off-by: NHoratiu Vultur <horatiu.vultur@microchip.com>

Microsemi SoC defines CONFIG_SYS_SDRAM_BASE to be 0x80000000, which
represents the start of kseg0 and represents a virtual address. Meaning
that the initrd_start and initrd_end point somewhere kseg0.
When these parameters are passed to linux kernel through DT
they are pointing somewhere in kseg0 which is a virtual address but linux
kernel expects the addresses to be physical addresses(in kuseg) because
it is converting the physical address to a virtual one.

Therefore update the uboot to pass the physical address of initrd_start
and initrd_end by converting them using the function virt_to_phys before
setting up the DT.
Signed-off-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

Remove "select MSCC_BITBANG_SPI_GPIO" since Kbuild option was deleted
back in commit ace9c103:

  commit ace9c103
  Author: Lars Povlsen <lars.povlsen@microchip.com>
  Date:   Tue Jan 8 10:38:35 2019 +0100

    mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.c

Add ethernet nodes for Serval SoCs family. There are 2 pcb in this
family: pcb105 and pcb106.
Signed-off-by: NHoratiu Vultur <horatiu.vultur@microchip.com>

In case the ddr training was failing, it couldn't reset, it was just
hanging. Therefore reimplement it, so when ddr training is failing
it would call _machine_restart, which power downs the DDR and does
a force reset.
Signed-off-by: NHoratiu Vultur <horatiu.vultur@microchip.com>

The card detect pin was incorrectly using IRQ_TYPE_LEVEL_LOW
instead of GPIO_ACTIVE_LOW when reading the state of the CD pin.

Without this patch, MMC1 won't be detected.

This is the same patch submitted to linux-omap, but I was hoping
to get it applied to U-Boot without having to wait for the
linux adoption and then backporting.

Fixes: 5448ff33 ("ARM: DTS: Resync Logic PD SOM-LV 37xx
devkit with Linux 4.18-RC4")
Signed-off-by: NAdam Ford <aford173@gmail.com>