- 08 5月, 2019 8 次提交
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由 Kever Yang 提交于
Move original spl to tpl, and add spl to load next stage firmware, adapt all the address and option for them. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
TPL stack may different from SPL and sys stack, add support for separate one when the board defines it. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
This reverts commit f338cca1. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
This is fix to: e2a12f590d rockchip: use 'arch-rockchip' as header file path The V2 of origin patch set has fix this, but we merge V1 by mistake, so lets correct it. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
boot0.h and gpio.h will be used by system and include by 'asm/arch/', each of them need of a copy from 'asm/arch-rockchip'. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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- 07 5月, 2019 16 次提交
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git://git.denx.de/u-boot-socfpga由 Tom Rini 提交于
- Assorted stratix10 fixes. - DDR driver DM migration.
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由 Chris Brandt 提交于
Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Chris Brandt 提交于
Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC. Distinguishing feature of this SoC is that it has up to 10 MiB of on-SoC static RAM (SRAM). The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add ifdeffery to allow operation without the clock framework enabled. This is required on RZ/A1, as it does not have clock driver yet. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add ifdeffery to allow operation without the clock framework enabled. This is required on RZ/A1, as it does not have clock driver yet. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add support for RZ/A1 SoC specifics. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add support for RZ/A1 SoC specifics. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add pin control driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add GPIO driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
There are no more boards using this CPU and there is no prospect of any boards showing up soon, remove it. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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由 Marek Vasut 提交于
Last change to this board was done in 2016, it uses non-DM USB with no prospects of ever being converted to DM USB, drop it. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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由 Marek Vasut 提交于
There are no more boards using this CPU and there is no prospect of any boards showing up soon, remove it. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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由 Marek Vasut 提交于
Last change to this board was done in 2016, it uses non-DM USB with no prospects of ever being converted to DM USB, drop it. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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由 Marek Vasut 提交于
Update the README to use the correct defconfig. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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- 06 5月, 2019 8 次提交
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由 Ang, Chee Hong 提交于
Send CONFIG_STATUS and RECONFIG_STATUS mailbox commands to Secure Device Manager (SDM) to get the status of FPGA and make sure the FPGA is in user mode before enable the bridge. Signed-off-by: NAng, Chee Hong <chee.hong.ang@intel.com>
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由 Ang, Chee Hong 提交于
Software must never reset FPGA2SOC bridge. This bridge must only be reset by POR/COLD/WARM reset. Asserting the FPGA2SOC reset by software can cause the SoC to lock-up if there are traffics being drived into FPGA2SOC bridge. Signed-off-by: NAng, Chee Hong <chee.hong.ang@intel.com>
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由 Ley Foon Tan 提交于
Convert Stratix 10 SDRAM driver to device model. Get rid of call to socfpga_per_reset() and use reset framework. SPL is changed from calling function in SDRAM driver directly to just probing UCLASS_RAM. Move sdram_s10.h from arch to driver/ddr/altera directory. Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>
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由 Ley Foon Tan 提交于
Add SDRAM device tree node. Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>
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由 Ley Foon Tan 提交于
Compile ALTERA_SDRAM driver in SPL only. Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM. Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>
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由 Tom Rini 提交于
- Various assorted fixes - btrfs zstd compression support - Enable hardware DDR levelling on am43xx platforms. - pl310 cache controller driver
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- 05 5月, 2019 8 次提交
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由 Philip Molloy 提交于
Signed-off-by: NPhilip Molloy <philip@philipmolloy.com>
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由 Marcel Ziswiler 提交于
Drop Toradex ARM Support <support.arm@toradex.com> from maintainer email list as this just clogs our support ticketing system. Signed-off-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: NStefan Agner <stefan.agner@toradex.com>
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由 Marek Behún 提交于
The list of PXE default paths contains ARCH and SOC specific paths, but one PXE server can serve different board with the same ARCH and SOC. This is the case for Turris Omnia and Turris Mox, where ARCH=arm and SOC=mvebu. If CONFIG_SYS_BOARD is defined, also try "default-$ARCH-$SOC-$BOARD" path. Signed-off-by: NMarek Behún <marek.behun@nic.cz>
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由 Adam Ford 提交于
The DA850 EVM has one USB 1.1 OHCI Host controller. With the host controller now support DM_USB, this patch enables the respective functions for the da850evm. Signed-off-by: NAdam Ford <aford173@gmail.com>
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由 Adam Ford 提交于
This patch reuses some former code for the hawkboard, combines it with some some similar DM_USB compatible code for the OHCI driver, and enables the use of the da850's OHCI controller with DM_USB compatibility. Signed-off-by: NAdam Ford <aford173@gmail.com>
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由 Marek Behún 提交于
This adds decompression support for Zstandard, which has been included in Linux btrfs driver for some time. Signed-off-by: NMarek Behún <marek.behun@nic.cz>
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由 Marek Behún 提交于
Add the zstd library from Linux kernel (only decompression support). There are minimal changes to build with U-Boot, otherwise the files are identical to Linux commit dc35da16 from March 2018, the files had not been touched since in kernel. Also SPDX lincese tags were added. Signed-off-by: NMarek Behún <marek.behun@nic.cz>
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由 Marek Behún 提交于
This adds the xxhash support from Linux. Files are almost identical to those added to Linux in commit 5d240522 ("lib: Add xxhash module") (they haven't been touched since in Linux). The only difference is to add some includes to be compatible with U-Boot. Also SPDX lincese tags were added. Signed-off-by: NMarek Behún <marek.behun@nic.cz>
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