- 21 4月, 2017 1 次提交
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由 Icenowy Zheng 提交于
Basic U-Boot support is now present for V3s. Some memory addresses are changed specially for V3s, as the original address map cannot fit into a so small DRAM. As the DRAM controller code needs a big refactor, the SPL support is disabled in this version. Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NJagan Teki <jagan@openedev.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 20 4月, 2017 25 次提交
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由 Jernej Skrabec 提交于
This is needed for HDMI, which will be added later. Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Jernej Skrabec 提交于
Video driver for older Allwinner SoCs uses cfb console framework which in turn uses struct ctfb_res_modes to hold timing informations. However, DM video framework uses different structure - struct display_timing. It makes more sense to convert lcdc to use new timing structure because all new drivers should use DM video framework and older drivers might be rewritten to use new framework too. Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Jernej Skrabec 提交于
TCON unit has similar layout and functionality also on newer SoCs. This commit splits out TCON code for easier reuse later. Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The Bananapi M2 Ultra is the first publicly available development board featuring the R40 SoC. This patch add barebone dtsi/dts files for the R40 and Bananapi M2 Ultra, as well as a defconfig for it. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The R40's CPU controls are a combination of sun6i and sun7i. All controls are in the CPUCFG block, and it seems the R40 does not have a PRCM block. The core reset, power gating and clamp controls are grouped like sun6i. Last, the R40 does not have a secure SRAM block. This patch adds a PSCI implementation for CPU bring-up and hotplug for the R40. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The R40 has the CPUCFG block at the same address as the A20. Fix it. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
Now that we can do DRAM initialization for the R40, we can enable SPL support for it. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The R40 seems to have a variant of the memory controller found in the H3 and A64 SoCs. Adapt the code for use on the R40. The changes are based on released DRAM code and comparing register dumps from boot0. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The PIO on the R40 SoC is mostly compatible with the A20. Only a few pin functions for mmc2 were added to the PC pingroup, to support 8 bit eMMCs. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
These values were taken from the Banana Pi M2 Ultra fex file found in the released vendor BSP. This is the only publicly available R40 device at the time of this writing. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has an extra "PLL lock control" register in the CCU, which controls whether the individual PLL lock status bits in each PLL's control register work or not. This patch enables it for all the PLLs. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The PIO is generally compatible with the A20, except that it routes the full 8 bits and eMMC reset pins for mmc2. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The watchdog found on the R40 SoC is the older variant found on the A20. Add the proper "#if defines" to make it work. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The R40 SoC uses the AXP221s in I2C mode to supply power. Some regulator's common usages have changed, and also the recommended voltage for existing usages have changed. Update the defaults to match. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The R40 is the successor to the A20. It is a hybrid of the A20, A33 and the H3. The R40's PIO controller is compatible with the A20, Reuse the A20 UART and I2C muxing code by adding the R40's macro. The display pipeline is the newer DE 2.0 variant. Block enabling video on R40 for now. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
Currently we have some lines in board/sunxi/Kconfig that are very long. These line either provide default values for a set of SoCs, or limit some option to a subset of sunxi SoCs. Fortunately Kconfig makes it easy to split them. The Kconfig language document states If multiple dependencies are defined, they are connected with '&&'. This means we can split existing dependencies at "&&" symbols. This applies to both the "depends on" lines and "if" expressions. This patch splits them up to one symbol per line. This will make it easier to add, remove, or modify one item at a time. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Mylène Josserand 提交于
Convert the CONS_INDEX configuration to Kconfig. Update sunxi's defconfigs to remove SYS_EXTRA_OPTIONS variable not needed anymore. Default value is 1 except for sun5i (equals 2) and sun8i (equals 5). Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com> [Maxime: Added a depends on ARCH_SUNXI to avoid build breakages] Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Mylène Josserand 提交于
Convert the CONFIG_MACPWR to Kconfig and update all the sunxi defconfigs that used it in SYS_EXTRA_OPTIONS. Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Mylène Josserand 提交于
Convert the CONFIG_SATAPWR into kconfig. Thanks to that, many SYS_EXTRA_OPTIONS can be removed from some defconfigs. Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Mylène Josserand 提交于
Convert CONFIG_RGMII to Kconfig. Thanks to that, it is possible to update defconfig files of SYS_EXTRA_OPTIONS accordingly and remove it when it is possible. Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Mylène Josserand 提交于
Convert the SUNXI_EMAC config to Kconfig. Remove it from SYS_EXTRA_OPTIONS from many sunxi defconfig and renamed it into SUN4I_EMAC to not confuse it with SUN8I_EMAC. Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Mylène Josserand 提交于
The USB_EHCI configuration is already set in this defconfig using kconfig's config. This configuration in SYS_EXTRA_OPTIONS must be removed and so the SYS_EXTRA_OPTIONS. Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Mylène Josserand 提交于
This configuration is not necessary in a defconfig file so it is removed from the SYS_EXTRA_OPTIONS. Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Mylène Josserand 提交于
Remove the AXP209_POWER option from SYS_EXTRA_OPTIONS. As this configuration already exists on Kconfig, we just need to remove it from defconfig. Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Mylène Josserand 提交于
Move the SUNXI_GMAC config option to Kconfig, remove it from SYS_EXTRA_OPTIONS and rename it into SUN7I_GMAC. Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 18 4月, 2017 2 次提交
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由 Jelle van der Waa 提交于
Add myself as maintainer of the NanoPi NEO Air board. Signed-off-by: NJelle van der Waa <jelle@vdwaa.nl> Reviewed-by: NJagan Teki <jagan@openedev.com>
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
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- 17 4月, 2017 2 次提交
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- 16 4月, 2017 10 次提交
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由 Philipp Tomsich 提交于
The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the serial line available via standardised pins on the edge connector and available on a RS232 connector). To support boards (such as the RK3399-Q7) that require UART0 as a debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate iomux setup to the rk3399 SPL code. As we are already touching this code, we also move the board-specific UART setup (i.e. iomux setup) into board_debug_uart_init(). This will be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT is set. As the RK3399 needs to use its board_debug_uart_init() function, we have Kconfig enable it by default for RK3399 builds. With everything set up to define CONFIG_BAUDRATE via defconfig and with to have the SPL debug UART either on UART0 or UART2, the configs for the RK3399 EVB are then update (the change for the RK3399-Q7 is left for later to not cause issues on applying the change). Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 eric.gao@rock-chips.com 提交于
For using mipi display, we need to enable lcd3v3 which supplied by rk808,so enable rk808 first. Signed-off-by: NEric Gao <eric.gao@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 eric.gao@rock-chips.com 提交于
To enable mipi display, we need to enable pmic rk808 first for lcd3v3 power,which use i2c0 to communicate with soc. So enable i2c0. Signed-off-by: NEric Gao <eric.gao@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 eric.gao@rock-chips.com 提交于
when enable PMIC rk808,the system will halt at very early stage,log is shown as bellow. INFO: plat_rockchip_pmu_init(1211): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9 time 44561b, 0 (<<----Just stop here) It's caused by the absence of "{ }" in syscon_rk3399.c ,which will lead to memory overflow like below.According to Sysmap file ,we can find the function buck_get_value of rk808 is just follow the compatible struct,the pointer "of_match" point to "buck_get_value",but it is not a struct and don't have member of compatible, In this case, system crash. So,on the face, it looks like that rk808 is guilty.but he is really innocent. while (of_match->compatible) { <<---------- if (!strcmp(of_match->compatible, compat)) { *of_idp = of_match; return 0; } of_match++; } Signed-off-by: NEric Gao <eric.gao@rock-chips.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com> Tested-by: NKever Yang <kever.yang@rock-chips.com>
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由 Klaus Goger 提交于
The RK3399-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230 connector) system-on-module from Theobroma Systems, featuring the Rockchip RK3399. It provides the following feature set: * up to 4GB DDR3 * on-module SPI-NOR flash * on-module eMMC (with 8-bit interace) * SD card (on a baseboad) via edge connector * Gigabit Ethernet w/ on-module Micrel KSZ9031 GbE PHY * HDMI/eDP/MIPI displays * 2x MIPI-CSI * USB - 1x USB 3.0 dual-role (direct connection) - 2x USB 3.0 host + 1x USB 2.0 (on-module USB 3.0 hub) * on-module STM32 Cortex-M0 companion controller, implementing: - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) - USB<->CAN bridge controller Note that we use a multi-payload FIT image for booting and have Cortex-M0 payload in a separate subimage: we thus rely on the FIT image loader to put it into the SRAM region that ATF expects it in. Signed-off-by: NKlaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Fixed build warning on puma-rk3399: Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
The RK3399-Q7 (Puma) DTS should (of course) be dual-licensed. This updates the licensing info in the rk3399-puma.dts. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Heiko Stübner 提交于
The warm-reset of rk3188 socs keeps the remap setting as it was, so if it was enabled, the cpu would start from address 0x0 of the sram instead of address 0x0 of the bootrom, thus making the reset hang. Therefore make sure the remap is disabled before attempting a warm reset. Cold reset is not affected by this at all. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
The lower address is reserved for ATF, do not use it. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Heiko Stübner 提交于
Most Rockchip socs have the ability to either map the bootrom or a sram area to the starting address of the cpu by flipping a bit in the GRF. Newer socs leave this untouched and mapped to the bootrom but the legacy loaders on rk3188 and before enabled the remap functionality and the current smp implementation in the Linux kernel also requires it to be enabled, to bring up secondary cpus. So to keep smp working in the kernel, mimic the behaviour of the legacy bootloaders and enable the remap functionality. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Heiko Stübner 提交于
Somehow 43b5c78d ("rockchip: cosmetic: Sort RK3288 boards") moved the rock board in between some rk3288 board, probably as a result of rebasing. So move it back to its original position above all rk3288 boards. Fixes: 43b5c78d ("rockchip: cosmetic: Sort RK3288 boards") Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NSimon Glass <sjg@chromium.org>
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