Add vdd_center pwm regulator get_device to
enable this regulator.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

add driver support for pwm regulator.
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Reference to kernel source code, rockchip pwm has three
type, we are using v2 for rk3288 and rk3399, so let's
update the register to sync with pwm_data_v2 in kernel.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Update PPLL to 676MHz and PMU_PCLK to 48MHz, because:
1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz
can not,
2. We think 48MHz is fast enough for pmu pclk and it is lower power cost
than 99MHz,
3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using
internally for kernel,it suppose not to change the bus clock like pmu_pclk
in kernel, so we want to change it in uboot.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Enable ums feature for rk3036 boards, so that we can mount the mmc
device to PC.
Signed-off-by: Njacob2.chen <jacob2.chen@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Rock2 has been tested with back to brom feature. The tricky part is that
with this feature the default environment is inside u-boot, and it's
defined for every rk3288 board independetly. So I just changed it for
rock2 here if ROCKCHIP_SPL_BACK_TO_BROM.

Solve by moving environment after u-boot before 1M boundary
Signed-off-by: NSandy Patterson <apatterson@sightlogix.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Default SPL_MMC_SUPPORT to false when ROCKCHIP_SPL_BACK_TO_BROM is enabled.
Acked-by: NZiyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: NSandy Patterson <apatterson@sightlogix.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Move back_to_bootrom() call later in SPL init so that the console is
initialized and printouts happen.

Currently when ROCKCHIP_SPL_BACK_TO_BROM is enabled there is no console
output from the SPL init stages.

I wasn't sure exactly where this should happen, so if we are set to do
run spl_board_init, then go back to bootrom there after
preloader_console_init(). Otherwise fall back to old behavior of doing
it in board_init_f.
Signed-off-by: NSandy Patterson <apatterson@sightlogix.com>
Acked-by: NZiyuan Xu <xzy.xu@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

The all current Rockchip SoCs supporting 4GB of ram have problems
accessing the memory region 0xfe000000~0xff000000. Actually, some IP
controller can't address to, so let's limit the available range.

This patch fixes a bug which found in miniarm-rk3288-4GB board. The
U-Boot was relocated to 0xfef72000, and .bss variants was also
relocated, such as do_fat_read_at_block. Once eMMC controller transfer
data to do_fat_read_at_block via DMA, DMAC can't access more than
0xfe000000. So that DMAC didn't work sane.
Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NTom Rini <trini@konsulko.com>

Conflicts:
	include/configs/dra7xx_evm.h

Enable pie option for relocation.
Signed-off-by: Nrick <rick@andestech.com>
Cc: Andes <uboot@andestech.com>

Apply the erratum A006261 for the following Socs:
P2041 rev 2.0, P2040 rev 2.0, P5040 rev 2.0, 2.1

Do not apply erratum A006261 for the following Socs:
T4160, T4080, T1040, T1042, T1020, T1022, T2080, T2081

Erratum A006261 is applicable for the following Socs:
P1010(1.0, 2.0), P2041(1.0, 1.1, 2.0, 2.1), P2040(1.0, 1.1, 2.0, 2.1),
P3041(1.0, 1.1, 2.0, 2.1), P5010(1.0, 2.0), P5020(1.0, 2.0),
P5021(1.0, 2.0), T4240(1.0, 2.0), P5040(1.0,2.0,2.1).
Signed-off-by: NSriram Dash <sriram.dash@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy
offset are set to enable the initial setting of Usb Phy for P1010.
Signed-off-by: NSriram Dash <sriram.dash@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Modifies erratum implementation due to the fact that P3041,
P5020, and P5040 are all big endian for the USB PHY registers, but
they were specified little endian.
Signed-off-by: NSriram Dash <sriram.dash@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Currently the controller by default enables the Receive Detect feature in P3
mode in USB 3.0 PHY. However, USB 3.0 PHY does not reliably support receive
detection in P3 mode.
Enabling the USB3 controller to configure USB in P2 mode whenever the Receive
Detect feature is required.
Signed-off-by: NSriram Dash <sriram.dash@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>

The functions fdt_fixup_erratum and fdt_fixup_usb_erratum are
fsl/nxp specific. So, make them explicit by renaming them
fsl_fdt_fixup_erratum and fsl_fdt_fixup_usb_erratum
Signed-off-by: NSriram Dash <sriram.dash@nxp.com>

The function fdt_fixup_dr_usb is specific to fsl/nxp. So,
make the function name explicit and rename fdt_fixup_dr_usb
into fsl_fdt_fixup_dr_usb.
Signed-off-by: NSriram Dash <sriram.dash@nxp.com>

Since commit aa7a6487
("net: Stop including NFS overhead in defragment max") the following
has been reproducibly observed while trying to transfer data over TFTP:

Load address: 0x80408000
Loading: EHCI timed out on TD - token=0x8008d80
T EHCI timed out on TD - token=0x88008d80
Rx: failed to receive: -5

This patch fixes this by lowering our TFTP block size to be within the
standard maximal de-fragmentation aka IP packet size again.
Signed-off-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com>

Enable USB driver model for Toradex Colibri Vybrid modules.
Signed-off-by: NSanchayan Maity <maitysanchayan@gmail.com>

Enable USB device tree node for Toradex Colibri Vybrid module.
Signed-off-by: NSanchayan Maity <maitysanchayan@gmail.com>

Add device tree node for USB peripheral on Vybrid.
Signed-off-by: NSanchayan Maity <maitysanchayan@gmail.com>

Add driver model support for Vybrid USB driver.
Signed-off-by: NSanchayan Maity <maitysanchayan@gmail.com>

Without this, if g_dnl_register() fails, DFU code continues on
blindly and crashes. This fix makes it simply print an error
message instead.
Signed-off-by: NSanchayan Maity <maitysanchayan@gmail.com>
[l.majewski@samsung.com - some manual tweaks needed]

This patch enables the SPL-DFU support for
dra7x platform.
Signed-off-by: NRavi Babu <ravibabu@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

This patch enables the DFU boot mode support
for dra7x platform.
Signed-off-by: NRavi Babu <ravibabu@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Adding support functions to run dfu spl commands.
Signed-off-by: NRavi Babu <ravibabu@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

The cmd_dfu functionality is been used by both SPL and
u-boot, saperating the core dfu functionality moving
it to common/dfu.c.
Signed-off-by: NRavi Babu <ravibabu@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Traditionally the DFU support is available only
as part 2nd stage boot loader(u-boot) and DFU
is not supported in SPL.

The SPL-DFU feature is useful for boards which
does not have MMC/SD, ethernet boot mechanism
to boot the board and only has USB inteface.

This patch add DFU support in SPL with RAM
memory device support to load and execute u-boot.
And then leverage full functionality DFU in
u-boot to flash boot inital binary images to
factory or bare-metal boards to memory devices
like SPI, eMMC, MMC/SD card using USB interface.

This SPL-DFU support can be enabled through
Menuconfig->Boot Images->Enable SPL-DFU support
Signed-off-by: NRavi Babu <ravibabu@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

This is required for better performance, and performs below tuning:
1. Enable burst length set, and define it as 4/8/16.
2. Set burst request limit to 16 requests.
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: NSriram Dash <sriram.dash@nxp.com>

Since commit aa7a6487
("net: Stop including NFS overhead in defragment max") the following
has been reproducibly observed while trying to transfer data over TFTP:

Load address: 0x80408000
Loading: EHCI timed out on TD - token=0x8008d80
T EHCI timed out on TD - token=0x88008d80
Rx: failed to receive: -5

This patch fixes this by upping our maximal de-fragmentation aka IP
packet size again.
Signed-off-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com>

Commit 14727120 ("net: asix: fix operation without eeprom")
added a special handling for ASIX 88772B that enable another
type of header. This break the driver in DM mode as the extra handling
needed in the receive path is missing.

However this new header mode is not required and only seems to
increase the code complexity, so this patch revert this part of
commit 14727120.

This also reverts commit 41d1258a
("net: asix: Fix AX88772B when used with DriverModel") of late.

Fixes: 14727120 ("net: asix: fix operation without eeprom")
Signed-off-by: NAlban Bedel <alban.bedel@avionic-design.de>
Signed-off-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com>

This board is getting close to or exceeding the size limit again, remove
CONFIG_AUTO_COMPLETE to save space and while in here switch to the
default and slightly less complete default baudrate table.

Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: NTom Rini <trini@konsulko.com>
Signed-off-by: NStefan Roese <sr@denx.de>

On Tegra186, it is necessary to perform an SMC to fully flush all caches;
flushing/cleaning by set/way is not enough. Implement the required hook
to make this happen.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Commit ce02a71c "tegra: dts: Sync tegra20 device tree files with
Linux" enabled the ULPI USB port on Ventana, but made no attempt to ensure
that U-Boot code could handle this. In practice, various code is missing,
and various configuration options are not enabled, which causes U-Boot to
hang when attempting to initialize this USB port. This patch enables ULPI
PHY support on Ventana, and adds the required pinmux setup for the port to
operate. Note that Ventana is so similar to Seaboard that this change is
made in the Seaboard board file, which is shared with Ventana.

Seaboard also has the ULPI USB port wired up in hardware, although to an
internal port that often doesn't have anything attached to it. However,
the DT nodes for the USB controller and PHY had different status property
values, so the port was not initialized by U-Boot. Fix this inconsistency,
and enable the ULPI port, just like in the Linux kernel DT. This likewise
requires enabling ULPI support in the Seaboard defconfig.

Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Some boards have a different set of USB controllers enabled in DT than
the set referenced by /alias entries. This patch fixes that. For
example, this avoids the following message while booting on Ventana,
which is caused by the fact that the USB0 controller had no alias, and
defaulted to wanting a sequence number of 0, which was later explicitly
requested by the alias for USB controller 2.

USB2:   Device 'usb@c5008000': seq 0 is in use by 'usb@c5000000'

This didn't affect USB operation in any way though.

Related, there's no need for the USB controller aliases to have an order
that's different from the HW order, so re-order any aliases to match the
HW ordering. This has the benefit that since USB controller 0 is the only
one that supports device-mode in HW, and U-Boot only supports enabling
device move on controller 0, there's now good synergy in the ordering! For
Tegra20, that's not relevant at present since USB device mode doesn't work
correctly on that SoC, but it will save some head-scratching later.

This patch doesn't fix the colibri_t20 board, even though it has the same
issue, since Marcel already sent a patch for that.

Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>
Tested-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Harmony and Ventana

USB ULPI PHY reset signals are typically active low. Consequently, they
should be marked as GPIO_ACTIVE_LOW in device tree, and indeed they are in
the Linux kernel DTs, and in DT properties that U-Boot doesn't yet use.
However, in DT properties that U-Boot does use, the value has been set to
0 (== GPIO_ACTIVE_HIGH) to work around a bug in U-Boot.

This change fixes the DT to correctly represent the HW, and fixes the
Tegra USB driver to cope with the fact that dm_gpio_set_value() internally
handles any inversions implied by the DT value GPIO_ACTIVE_LOW.

Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Now that the standard clock/reset APIs are available for all Tegra SoCs,
convert the I2C driver to use them exclusively, and remove any references
to the custom Tegra-specific APIs.

Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>