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提交 40e1236a 编写于 作者: T Tom Rini
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Merge branch 'master' of git://git.denx.de/u-boot-tegra

上级 6d556560 8e5d804f
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Showing with 3555 addition and 1235 deletion
arch/arm/dts/tegra114-dalmore.dts
浏览文件 @ 40e1236a
......@@ -16,8 +16,8 @@
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
sdhci0 = "/sdhci@78000600";
sdhci1 = "/sdhci@78000400";
mmc0 = "/sdhci@78000600";
mmc1 = "/sdhci@78000400";
usb0 = "/usb@7d000000";
usb1 = "/usb@7d008000";
};
......@@ -66,6 +66,7 @@
sdhci@78000600 {
bus-width = <8>;
status = "okay";
non-removable;
};
usb@7d000000 {
......@@ -78,4 +79,17 @@
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
status = "okay";
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
};
arch/arm/dts/tegra114.dtsi
浏览文件 @ 40e1236a
此差异已折叠。
arch/arm/dts/tegra124-cei-tk1-som.dts
浏览文件 @ 40e1236a
......@@ -16,8 +16,8 @@
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
sdhci0 = "/sdhci@700b0600";
sdhci1 = "/sdhci@700b0400";
mmc0 = "/sdhci@700b0600";
mmc1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
usb0 = "/usb@7d000000";
......
arch/arm/dts/tegra124-jetson-tk1.dts
浏览文件 @ 40e1236a
......@@ -16,8 +16,8 @@
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
sdhci0 = "/sdhci@700b0600";
sdhci1 = "/sdhci@700b0400";
mmc0 = "/sdhci@700b0600";
mmc1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
usb0 = "/usb@7d000000";
......@@ -312,6 +312,7 @@
sdhci@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
};
usb@7d000000 {
......
arch/arm/dts/tegra124-nyan-big.dts
浏览文件 @ 40e1236a
......@@ -15,10 +15,10 @@
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
i2c5 = "/i2c@7000d100";
rtc0 = "/i2c@0,7000d000/pmic@40";
rtc1 = "/rtc@0,7000e000";
sdhci0 = "/sdhci@700b0600";
sdhci1 = "/sdhci@700b0400";
rtc0 = "/i2c@7000d000/pmic@40";
rtc1 = "/rtc@7000e000";
mmc0 = "/sdhci@700b0600";
mmc1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
usb0 = "/usb@7d000000";
......@@ -58,7 +58,7 @@
ddc-i2c-bus = <&dpaux>;
};
sdhci@0,700b0400 { /* SD Card on this bus */
sdhci@700b0400 { /* SD Card on this bus */
wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
};
......@@ -69,7 +69,7 @@
nvidia,model = "GoogleNyanBig";
};
pinmux@0,70000868 {
pinmux@70000868 {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_default>;
......
arch/arm/dts/tegra124-nyan.dtsi
浏览文件 @ 40e1236a
......@@ -3,8 +3,8 @@
/ {
aliases {
rtc0 = "/i2c@0,7000d000/pmic@40";
rtc1 = "/rtc@0,7000e000";
rtc0 = "/i2c@7000d000/pmic@40";
rtc1 = "/rtc@7000e000";
serial0 = &uarta;
};
......@@ -424,10 +424,12 @@
usb@7d004000 { /* Internal webcam. */
status = "okay";
phy_type = "hsic";
};
usb-phy@7d004000 {
status = "okay";
phy_type = "hsic";
vbus-supply = <&vdd_run_cam>;
};
......
arch/arm/dts/tegra124-venice2.dts
浏览文件 @ 40e1236a
......@@ -17,8 +17,8 @@
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
i2c5 = "/i2c@7000d100";
sdhci0 = "/sdhci@700b0600";
sdhci1 = "/sdhci@700b0400";
mmc0 = "/sdhci@700b0600";
mmc1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
usb0 = "/usb@7d000000";
......@@ -81,6 +81,7 @@
sdhci@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
};
usb@7d000000 {
......
arch/arm/dts/tegra124.dtsi
浏览文件 @ 40e1236a
......@@ -196,13 +196,18 @@
lic: interrupt-controller@60004000 {
compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
reg = <0x0 0x60004000 0x0 0x100>,
<0x0 0x60004100 0x0 0x100>,
<0x0 0x60004200 0x0 0x100>,
<0x0 0x60004300 0x0 0x100>,
<0x0 0x60004400 0x0 0x100>;
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
};
timer@60005000 {
compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
reg = <0x60005000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
......@@ -316,7 +321,7 @@
* driver and APB DMA based serial driver for higher baudrate
* and performace. To enable the 8250 based driver, the compatible
* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
* the APB DMA based serial driver, the comptible is
* the APB DMA based serial driver, the compatible is
* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
*/
uarta: serial@70006000 {
......@@ -399,10 +404,15 @@
i2c@7000c400 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000c400 0x100>;
interrupts = <0 84 0x04>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 54>;
clocks = <&tegra_car TEGRA124_CLK_I2C2>;
clock-names = "div-clk";
resets = <&tegra_car 54>;
reset-names = "i2c";
dmas = <&apbdma 22>, <&apbdma 22>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -631,6 +641,41 @@
status = "disabled";
};
usb@70090000 {
compatible = "nvidia,tegra124-xusb";
reg = <0x70090000 0x8000>,
<0x70098000 0x1000>,
<0x70099000 0x1000>;
reg-names = "hcd", "fpci", "ipfs";
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
<&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_SS>,
<&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
<&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
<&tegra_car TEGRA124_CLK_PLL_U_480M>,
<&tegra_car TEGRA124_CLK_CLK_M>,
<&tegra_car TEGRA124_CLK_PLL_E>;
clock-names = "xusb_host", "xusb_host_src",
"xusb_falcon_src", "xusb_ss",
"xusb_ss_div2", "xusb_ss_src",
"xusb_hs_src", "xusb_fs_src",
"pll_u_480m", "clk_m", "pll_e";
resets = <&tegra_car 89>, <&tegra_car 156>,
<&tegra_car 143>;
reset-names = "xusb_host", "xusb_ss", "xusb_src";
nvidia,xusb-padctl = <&padctl>;
status = "disabled";
};
padctl: padctl@7009f000 {
compatible = "nvidia,tegra124-xusb-padctl";
reg = <0x7009f000 0x1000>;
......@@ -820,7 +865,7 @@
};
usb@7d000000 {
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x7d000000 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
......@@ -857,10 +902,10 @@
};
usb@7d004000 {
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x7d004000 0x4000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "hsic";
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USB2>;
resets = <&tegra_car 58>;
reset-names = "usb";
......
arch/arm/dts/tegra186-p2771-0000.dtsi
浏览文件 @ 40e1236a
......@@ -9,8 +9,8 @@
};
aliases {
sdhci0 = "/sdhci@3460000";
sdhci1 = "/sdhci@3400000";
mmc0 = "/sdhci@3460000";
mmc1 = "/sdhci@3400000";
i2c0 = "/bpmp/i2c";
i2c1 = "/i2c@3160000";
i2c2 = "/i2c@c240000";
......@@ -50,6 +50,7 @@
sdhci@3460000 {
status = "okay";
bus-width = <8>;
non-removable;
};
i2c@c240000 {
......
arch/arm/dts/tegra20-colibri.dts
浏览文件 @ 40e1236a
......@@ -17,7 +17,7 @@
usb0 = "/usb@c5008000";
usb1 = "/usb@c5000000";
usb2 = "/usb@c5004000";
sdhci0 = "/sdhci@c8000600";
mmc0 = "/sdhci@c8000600";
};
host1x@50000000 {
......@@ -39,7 +39,8 @@
usb@c5004000 {
statuc = "okay";
/* VBUS_LAN */
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
};
......
arch/arm/dts/tegra20-harmony.dts
浏览文件 @ 40e1236a
......@@ -15,10 +15,11 @@
rtc0 = "/i2c@7000d000/tps6586x@34";
rtc1 = "/rtc@7000e000";
serial0 = &uartd;
usb0 = "/usb@c5008000";
usb0 = "/usb@c5000000";
usb1 = "/usb@c5004000";
sdhci0 = "/sdhci@c8000600";
sdhci1 = "/sdhci@c8000200";
usb2 = "/usb@c5008000";
mmc0 = "/sdhci@c8000600";
mmc1 = "/sdhci@c8000200";
};
memory {
......@@ -626,7 +627,8 @@
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
};
usb-phy@c5004000 {
......
arch/arm/dts/tegra20-medcom-wide.dts
浏览文件 @ 40e1236a
......@@ -12,7 +12,7 @@
aliases {
usb0 = "/usb@c5008000";
sdhci0 = "/sdhci@c8000600";
mmc0 = "/sdhci@c8000600";
};
memory {
......
arch/arm/dts/tegra20-paz00.dts
浏览文件 @ 40e1236a
......@@ -12,8 +12,8 @@
aliases {
usb0 = "/usb@c5008000";
sdhci0 = "/sdhci@c8000600";
sdhci1 = "/sdhci@c8000000";
mmc0 = "/sdhci@c8000600";
mmc1 = "/sdhci@c8000000";
};
memory {
......@@ -50,6 +50,7 @@
sdhci@c8000600 {
status = "okay";
bus-width = <8>;
non-removable;
};
clocks {
......
arch/arm/dts/tegra20-plutux.dts
浏览文件 @ 40e1236a
......@@ -12,7 +12,7 @@
aliases {
usb0 = "/usb@c5008000";
sdhci0 = "/sdhci@c8000600";
mmc0 = "/sdhci@c8000600";
};
memory {
......
arch/arm/dts/tegra20-seaboard.dts
浏览文件 @ 40e1236a
......@@ -9,8 +9,9 @@
aliases {
/* This defines the order of our ports */
usb0 = "/usb@c5008000";
usb1 = "/usb@c5000000";
usb0 = "/usb@c5000000";
usb1 = "/usb@c5004000";
usb2 = "/usb@c5008000";
i2c0 = "/i2c@7000d000";
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c400";
......@@ -18,8 +19,8 @@
rtc0 = "/i2c@7000d000/tps6586x@34";
rtc1 = "/rtc@7000e000";
serial0 = &uartd;
sdhci0 = "/sdhci@c8000600";
sdhci1 = "/sdhci@c8000400";
mmc0 = "/sdhci@c8000600";
mmc1 = "/sdhci@c8000400";
};
chosen {
......@@ -783,7 +784,7 @@
};
usb@c5004000 {
status = "disabled";
status = "okay";
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
};
......
arch/arm/dts/tegra20-tec.dts
浏览文件 @ 40e1236a
......@@ -12,7 +12,7 @@
aliases {
usb0 = "/usb@c5008000";
sdhci0 = "/sdhci@c8000600";
mmc0 = "/sdhci@c8000600";
};
memory {
......
arch/arm/dts/tegra20-trimslice.dts
浏览文件 @ 40e1236a
......@@ -11,10 +11,9 @@
};
aliases {
usb0 = "/usb@c5008000";
usb1 = "/usb@c5000000";
sdhci0 = "/sdhci@c8000600";
sdhci1 = "/sdhci@c8000000";
usb0 = "/usb@c5000000";
mmc0 = "/sdhci@c8000600";
mmc1 = "/sdhci@c8000000";
spi0 = "/spi@7000c380";
};
......
arch/arm/dts/tegra20-ventana.dts
浏览文件 @ 40e1236a
......@@ -15,9 +15,11 @@
rtc0 = "/i2c@7000d000/tps6586x@34";
rtc1 = "/rtc@7000e000";
serial0 = &uartd;
usb0 = "/usb@c5008000";
sdhci0 = "/sdhci@c8000600";
sdhci1 = "/sdhci@c8000400";
usb0 = "/usb@c5000000";
usb1 = "/usb@c5004000";
usb2 = "/usb@c5008000";
mmc0 = "/sdhci@c8000600";
mmc1 = "/sdhci@c8000400";
};
memory {
......
arch/arm/dts/tegra20-whistler.dts
浏览文件 @ 40e1236a
......@@ -13,8 +13,8 @@
aliases {
i2c0 = "/i2c@7000d000";
usb0 = "/usb@c5008000";
sdhci0 = "/sdhci@c8000600";
sdhci1 = "/sdhci@c8000400";
mmc0 = "/sdhci@c8000600";
mmc1 = "/sdhci@c8000400";
};
memory {
......@@ -58,6 +58,7 @@
sdhci@c8000600 {
status = "okay";
bus-width = <8>;
non-removable;
};
clocks {
......
arch/arm/dts/tegra20.dtsi
浏览文件 @ 40e1236a
......@@ -147,7 +147,7 @@
interrupt-parent = <&intc>;
reg = <0x50040600 0x20>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
clocks = <&tegra_car TEGRA20_CLK_TWD>;
};
......@@ -311,7 +311,7 @@
* driver and APB DMA based serial driver for higher baudrate
* and performace. To enable the 8250 based driver, the compatible
* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
* driver, the comptible is "nvidia,tegra20-hsuart".
* driver, the compatible is "nvidia,tegra20-hsuart".
*/
uarta: serial@70006000 {
compatible = "nvidia,tegra20-uart";
......
arch/arm/dts/tegra210-e2220-1170.dts
浏览文件 @ 40e1236a
......@@ -11,34 +11,35 @@
};
aliases {
i2c0 = "/i2c@0,7000d000";
sdhci0 = "/sdhci@0,700b0600";
sdhci1 = "/sdhci@0,700b0000";
usb0 = "/usb@0,7d000000";
i2c0 = "/i2c@7000d000";
mmc0 = "/sdhci@700b0600";
mmc1 = "/sdhci@700b0000";
usb0 = "/usb@7d000000";
};
memory {
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
sdhci@0,700b0000 {
sdhci@700b0000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
sdhci@0,700b0600 {
sdhci@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
};
i2c@0,7000d000 {
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
};
usb@0,7d000000 {
usb@7d000000 {
status = "okay";
dr_mode = "peripheral";
};
......
arch/arm/dts/tegra210-p2371-0000.dts
浏览文件 @ 40e1236a
......@@ -11,34 +11,35 @@
};
aliases {
i2c0 = "/i2c@0,7000d000";
sdhci0 = "/sdhci@0,700b0600";
sdhci1 = "/sdhci@0,700b0000";
usb0 = "/usb@0,7d000000";
i2c0 = "/i2c@7000d000";
mmc0 = "/sdhci@700b0600";
mmc1 = "/sdhci@700b0000";
usb0 = "/usb@7d000000";
};
memory {
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
sdhci@0,700b0000 {
sdhci@700b0000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
sdhci@0,700b0600 {
sdhci@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
};
i2c@0,7000d000 {
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
};
usb@0,7d000000 {
usb@7d000000 {
status = "okay";
dr_mode = "otg";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
......
arch/arm/dts/tegra210-p2371-2180.dts
浏览文件 @ 40e1236a
......@@ -11,17 +11,17 @@
};
aliases {
i2c0 = "/i2c@0,7000d000";
sdhci0 = "/sdhci@0,700b0600";
sdhci1 = "/sdhci@0,700b0000";
usb0 = "/usb@0,7d000000";
i2c0 = "/i2c@7000d000";
mmc0 = "/sdhci@700b0600";
mmc1 = "/sdhci@700b0000";
usb0 = "/usb@7d000000";
};
memory {
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
pcie-controller@0,01003000 {
pcie-controller@01003000 {
status = "okay";
pci@1,0 {
......@@ -33,7 +33,7 @@
};
};
padctl@0,7009f000 {
padctl@7009f000 {
pinctrl-0 = <&padctl_default>;
pinctrl-names = "default";
......@@ -71,7 +71,7 @@
};
};
sdhci@0,700b0000 {
sdhci@700b0000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
......@@ -79,17 +79,18 @@
bus-width = <4>;
};
sdhci@0,700b0600 {
sdhci@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
};
i2c@0,7000d000 {
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
};
usb@0,7d000000 {
usb@7d000000 {
status = "okay";
dr_mode = "otg";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
......
arch/arm/dts/tegra210-p2571.dts
浏览文件 @ 40e1236a
......@@ -11,82 +11,83 @@
};
aliases {
i2c0 = "/i2c@0,7000d000";
i2c1 = "/i2c@0,7000c000";
i2c2 = "/i2c@0,7000c400";
i2c3 = "/i2c@0,7000c500";
i2c4 = "/i2c@0,7000c700";
i2c5 = "/i2c@0,7000d100";
sdhci0 = "/sdhci@0,700b0600";
sdhci1 = "/sdhci@0,700b0000";
spi0 = "/spi@0,7000d400";
spi1 = "/spi@0,7000da00";
spi2 = "/spi@0,70410000";
usb0 = "/usb@0,7d000000";
i2c0 = "/i2c@7000d000";
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
i2c5 = "/i2c@7000d100";
mmc0 = "/sdhci@700b0600";
mmc1 = "/sdhci@700b0000";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
spi2 = "/spi@70410000";
usb0 = "/usb@7d000000";
};
memory {
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
i2c@0,7000c000 {
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
};
i2c@0,7000c400 {
i2c@7000c400 {
status = "okay";
clock-frequency = <100000>;
};
i2c@0,7000c500 {
i2c@7000c500 {
status = "okay";
clock-frequency = <100000>;
};
i2c@0,7000c700 {
i2c@7000c700 {
status = "okay";
clock-frequency = <100000>;
};
i2c@0,7000d000 {
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
};
i2c@0,7000d100 {
i2c@7000d100 {
status = "okay";
clock-frequency = <400000>;
};
spi@0,7000d400 {
spi@7000d400 {
status = "okay";
spi-max-frequency = <25000000>;
};
spi@0,7000da00 {
spi@7000da00 {
status = "okay";
spi-max-frequency = <25000000>;
};
spi@0,70410000 {
spi@70410000 {
status = "okay";
spi-max-frequency = <24000000>;
};
sdhci@0,700b0000 {
sdhci@700b0000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
sdhci@0,700b0600 {
sdhci@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
};
usb@0,7d000000 {
usb@7d000000 {
status = "okay";
dr_mode = "otg";
};
......
arch/arm/dts/tegra210.dtsi
浏览文件 @ 40e1236a
此差异已折叠。
arch/arm/dts/tegra30-apalis.dts
浏览文件 @ 40e1236a
......@@ -15,9 +15,9 @@
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c500";
i2c3 = "/i2c@7000c700";
sdhci0 = "/sdhci@78000600";
sdhci1 = "/sdhci@78000400";
sdhci2 = "/sdhci@78000000";
mmc0 = "/sdhci@78000600";
mmc1 = "/sdhci@78000400";
mmc2 = "/sdhci@78000000";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000dc00";
spi2 = "/spi@7000de00";
......@@ -277,7 +277,6 @@
status = "okay";
/* USBH_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
phy_type = "utmi";
};
/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
......@@ -287,6 +286,26 @@
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clk@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
clk16m: clk@1 {
compatible = "fixed-clock";
reg=<1>;
#clock-cells = <0>;
clock-frequency = <16000000>;
clock-output-names = "clk16m";
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
......
arch/arm/dts/tegra30-beaver.dts
浏览文件 @ 40e1236a
......@@ -16,8 +16,8 @@
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
sdhci0 = "/sdhci@78000600";
sdhci1 = "/sdhci@78000000";
mmc0 = "/sdhci@78000600";
mmc1 = "/sdhci@78000000";
spi0 = "/spi@7000da00";
usb0 = "/usb@7d000000";
usb1 = "/usb@7d008000";
......@@ -205,6 +205,7 @@
sdhci@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
};
usb@7d000000 {
......@@ -218,6 +219,19 @@
status = "okay";
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
......
arch/arm/dts/tegra30-cardhu.dts
浏览文件 @ 40e1236a
......@@ -16,8 +16,8 @@
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
sdhci0 = "/sdhci@78000600";
sdhci1 = "/sdhci@78000000";
mmc0 = "/sdhci@78000600";
mmc1 = "/sdhci@78000000";
spi0 = "/spi@7000da00";
usb0 = "/usb@7d008000";
};
......@@ -194,6 +194,7 @@
sdhci@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
};
usb@7d008000 {
......@@ -201,6 +202,19 @@
status = "okay";
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
......
arch/arm/dts/tegra30-colibri.dts
浏览文件 @ 40e1236a
......@@ -14,8 +14,8 @@
i2c0 = "/i2c@7000d000";
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c700";
sdhci0 = "/sdhci@78000600";
sdhci1 = "/sdhci@78000200";
mmc0 = "/sdhci@78000600";
mmc1 = "/sdhci@78000200";
spi0 = "/spi@7000d400";
usb0 = "/usb@7d000000";
usb1 = "/usb@7d004000"; /* on module only, for ASIX */
......@@ -84,7 +84,6 @@
status = "okay";
/* VBUS_LAN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
phy_type = "utmi";
};
/* EHCI instance 2: USB3_DP/N -> USBH_P/N */
......@@ -93,4 +92,17 @@
/* USBH_PEN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clk@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
};
arch/arm/dts/tegra30-tamonten.dtsi
浏览文件 @ 40e1236a
......@@ -18,9 +18,9 @@
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000d000";
sdhci0 = "/sdhci@78000600";
sdhci1 = "/sdhci@78000400";
sdhci2 = "/sdhci@78000000";
mmc0 = "/sdhci@78000600";
mmc1 = "/sdhci@78000400";
mmc2 = "/sdhci@78000000";
usb0 = "/usb@7d008000";
};
......@@ -64,10 +64,23 @@
sdhci@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
};
usb@7d008000 {
status = "okay";
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clk@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
};
arch/arm/dts/tegra30.dtsi
浏览文件 @ 40e1236a
此差异已折叠。
arch/arm/include/asm/arch-tegra/clock.h
浏览文件 @ 40e1236a
......@@ -186,6 +186,16 @@ int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
unsigned divisor);
/**
* Returns the current parent clock ID of a given peripheral. This can be
* useful in order to call clock_*_periph_*() from generic code that has no
* specific knowledge of system-level clock tree structure.
*
* @param periph_id peripheral to query
* @return clock ID of the peripheral's current parent clock
*/
enum clock_id clock_get_periph_parent(enum periph_id periph_id);
/**
* Start a peripheral PLL clock at the given rate. This also resets the
* peripheral.
......@@ -284,6 +294,36 @@ u32 *get_periph_source_reg(enum periph_id periph_id);
/* Returns a pointer to the given 'simple' PLL */
struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid);
/*
* Given a peripheral ID, determine where the mux bits are in the peripheral
* clock's register, the number of divider bits the clock has, and the SoC-
* specific clock type.
*
* This is an internal API between the core Tegra clock code and the SoC-
* specific clock code.
*
* @param periph_id peripheral to query
* @param mux_bits Set to number of bits in mux register
* @param divider_bits Set to the relevant MASK_BITS_* value
* @param type Set to the SoC-specific clock type
* @return 0 on success, -1 on error
*/
int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
int *divider_bits, int *type);
/*
* Given a peripheral ID and clock source mux value, determine the clock_id
* of that peripheral's parent.
*
* This is an internal API between the core Tegra clock code and the SoC-
* specific clock code.
*
* @param periph_id peripheral to query
* @param source raw clock source mux value
* @return the CLOCK_ID_* value @source represents
*/
enum clock_id get_periph_clock_id(enum periph_id periph_id, int source);
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
......@@ -362,6 +402,12 @@ struct clk_pll_info {
};
extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT];
struct periph_clk_init {
enum periph_id periph_id;
enum clock_id parent_clock_id;
};
extern struct periph_clk_init periph_clk_init_table[];
/**
* Enable output clock for external peripherals
*
......
arch/arm/include/asm/arch-tegra/mmc.h 已删除 100644 → 0
浏览文件 @ 6d556560
/*
* Copyright (c) 2011, Google Inc. All rights reserved.
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA_MMC_H_
#define _TEGRA_MMC_H_
void tegra_mmc_init(void);
#endif /* _TEGRA_MMC_H_ */
arch/arm/include/asm/arch-tegra/tegra_mmc.h
浏览文件 @ 40e1236a
......@@ -132,26 +132,5 @@ struct tegra_mmc {
#define AUTO_CAL_PD_OFFSET (0x70 << 8)
#define AUTO_CAL_PU_OFFSET (0x62 << 0)
struct mmc_host {
struct tegra_mmc *reg;
int id; /* device id/number, 0-3 */
int enabled; /* 1 to enable, 0 to disable */
int width; /* Bus Width, 1, 4 or 8 */
#ifdef CONFIG_TEGRA186
struct reset_ctl reset_ctl;
struct clk clk;
#else
enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
#endif
struct gpio_desc cd_gpio; /* Change Detect GPIO */
struct gpio_desc pwr_gpio; /* Power GPIO */
struct gpio_desc wp_gpio; /* Write Protect GPIO */
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
struct mmc_config cfg; /* mmc configuration */
};
void pad_init_mmc(struct mmc_host *host);
#endif /* __ASSEMBLY__ */
#endif /* __TEGRA_MMC_H_ */
arch/arm/mach-tegra/Kconfig
浏览文件 @ 40e1236a
......@@ -22,20 +22,30 @@ config TEGRA_IVC
config TEGRA_COMMON
bool "Tegra common options"
select CLK
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_KEYBOARD
select DM_MMC
select DM_PCI
select DM_PCI_COMPAT
select DM_PWM
select DM_RESET
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select MISC
select OF_CONTROL
select VIDCONSOLE_AS_LCD if DM_VIDEO
config TEGRA_NO_BPMP
bool "Tegra common options for SoCs without BPMP"
select TEGRA_CAR
select TEGRA_CAR_CLOCK
select TEGRA_CAR_RESET
config TEGRA_ARMV7_COMMON
bool "Tegra 32-bit common options"
select CPU_V7
......@@ -43,6 +53,7 @@ config TEGRA_ARMV7_COMMON
select SUPPORT_SPL
select TEGRA_COMMON
select TEGRA_GPIO
select TEGRA_NO_BPMP
config TEGRA_ARMV8_COMMON
bool "Tegra 64-bit common options"
......@@ -73,13 +84,11 @@ config TEGRA210
bool "Tegra210 family"
select TEGRA_GPIO
select TEGRA_ARMV8_COMMON
select TEGRA_NO_BPMP
config TEGRA186
bool "Tegra186 family"
select CLK
select DM_MAILBOX
select DM_RESET
select MISC
select TEGRA186_BPMP
select TEGRA186_CLOCK
select TEGRA186_GPIO
......
arch/arm/mach-tegra/board186.c
浏览文件 @ 40e1236a
......@@ -6,8 +6,6 @@
#include <common.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/mmc.h>
#include <asm/arch-tegra/tegra_mmc.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -30,14 +28,3 @@ int board_late_init(void)
{
return 0;
}
void pad_init_mmc(struct mmc_host *host)
{
}
int board_mmc_init(bd_t *bd)
{
tegra_mmc_init();
return 0;
}
arch/arm/mach-tegra/board2.c
浏览文件 @ 40e1236a
......@@ -32,10 +32,6 @@
#ifdef CONFIG_USB_EHCI_TEGRA
#include <usb.h>
#endif
#ifdef CONFIG_TEGRA_MMC
#include <asm/arch-tegra/tegra_mmc.h>
#include <asm/arch-tegra/mmc.h>
#endif
#include <asm/arch-tegra/xusb-padctl.h>
#include <power/as3722.h>
#include <i2c.h>
......@@ -54,6 +50,7 @@ U_BOOT_DEVICE(tegra_gpios) = {
__weak void pinmux_init(void) {}
__weak void pin_mux_usb(void) {}
__weak void pin_mux_spi(void) {}
__weak void pin_mux_mmc(void) {}
__weak void gpio_early_init_uart(void) {}
__weak void pin_mux_display(void) {}
__weak void start_cpu_fan(void) {}
......@@ -128,6 +125,10 @@ int board_init(void)
pin_mux_spi();
#endif
#ifdef CONFIG_TEGRA_MMC
pin_mux_mmc();
#endif
/* Init is handled automatically in the driver-model case */
#if defined(CONFIG_DM_VIDEO)
pin_mux_display();
......@@ -230,54 +231,6 @@ int board_late_init(void)
return 0;
}
#if defined(CONFIG_TEGRA_MMC)
__weak void pin_mux_mmc(void)
{
}
/* this is a weak define that we are overriding */
int board_mmc_init(bd_t *bd)
{
debug("%s called\n", __func__);
/* Enable muxes, etc. for SDMMC controllers */
pin_mux_mmc();
debug("%s: init MMC\n", __func__);
tegra_mmc_init();
return 0;
}
void pad_init_mmc(struct mmc_host *host)
{
#if defined(CONFIG_TEGRA30)
enum periph_id id = host->mmc_id;
u32 val;
debug("%s: sdmmc address = %08x, id = %d\n", __func__,
(unsigned int)host->reg, id);
/* Set the pad drive strength for SDMMC1 or 3 only */
if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
__func__);
return;
}
val = readl(&host->reg->sdmemcmppadctl);
val &= 0xFFFFFFF0;
val |= MEMCOMP_PADCTRL_VREF;
writel(val, &host->reg->sdmemcmppadctl);
val = readl(&host->reg->autocalcfg);
val &= 0xFFFF0000;
val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
writel(val, &host->reg->autocalcfg);
#endif /* T30 */
}
#endif /* MMC */
/*
* In some SW environments, a memory carve-out exists to house a secure
* monitor, a trusted OS, and/or various statically allocated media buffers.
......
arch/arm/mach-tegra/clock.c
浏览文件 @ 40e1236a
......@@ -206,6 +206,29 @@ int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
return 0;
}
static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits)
{
u32 *reg = get_periph_source_reg(periph_id);
u32 val = readl(reg);
switch (mux_bits) {
case MASK_BITS_31_30:
val >>= OUT_CLK_SOURCE_31_30_SHIFT;
val &= OUT_CLK_SOURCE_31_30_MASK;
return val;
case MASK_BITS_31_29:
val >>= OUT_CLK_SOURCE_31_29_SHIFT;
val &= OUT_CLK_SOURCE_31_29_MASK;
return val;
case MASK_BITS_31_28:
val >>= OUT_CLK_SOURCE_31_28_SHIFT;
val &= OUT_CLK_SOURCE_31_28_MASK;
return val;
default:
return -1;
}
}
void clock_ll_set_source(enum periph_id periph_id, unsigned source)
{
clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
......@@ -288,9 +311,43 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id,
enum clock_id parent)
{
u32 *reg = get_periph_source_reg(periph_id);
unsigned parent_rate = pll_rate[parent];
int div = (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT;
switch (periph_id) {
case PERIPH_ID_UART1:
case PERIPH_ID_UART2:
case PERIPH_ID_UART3:
case PERIPH_ID_UART4:
case PERIPH_ID_UART5:
#ifdef CONFIG_TEGRA20
/* There's no divider for these clocks in this SoC. */
return parent_rate;
#else
/*
* This undoes the +2 in get_rate_from_divider() which I
* believe is incorrect. Ideally we would fix
* get_rate_from_divider(), but... Removing the +2 from
* get_rate_from_divider() would probably require remove the -2
* from the tail of clk_get_divider() since I believe that's
* only there to invert get_rate_from_divider()'s +2. Observe
* how find_best_divider() uses those two functions together.
* However, doing so breaks other stuff, such as Seaboard's
* display, likely due to clock_set_pllout()'s call to
* clk_get_divider(). Attempting to fix that by making
* clock_set_pllout() subtract 2 from clk_get_divider()'s
* return value doesn't help. In summary this clock driver is
* quite broken but I'm afraid I have no idea how to fix it
* without completely replacing it.
*/
div -= 2;
break;
#endif
default:
break;
}
return get_rate_from_divider(pll_rate[parent],
(readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
return get_rate_from_divider(parent_rate, div);
}
/**
......@@ -363,6 +420,20 @@ static int adjust_periph_pll(enum periph_id periph_id, int source,
return 0;
}
enum clock_id clock_get_periph_parent(enum periph_id periph_id)
{
int err, mux_bits, divider_bits, type;
int source;
err = get_periph_clock_info(periph_id, &mux_bits, &divider_bits, &type);
if (err)
return CLOCK_ID_NONE;
source = clock_ll_get_source_bits(periph_id, mux_bits);
return get_periph_clock_id(periph_id, source);
}
unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
enum clock_id parent, unsigned rate, int *extra_div)
{
......@@ -612,6 +683,8 @@ int clock_verify(void)
void clock_init(void)
{
int i;
pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
......@@ -630,6 +703,19 @@ void clock_init(void)
debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);
debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) {
enum periph_id periph_id;
enum clock_id parent;
int source, mux_bits, divider_bits;
periph_id = periph_clk_init_table[i].periph_id;
parent = periph_clk_init_table[i].parent_clock_id;
source = get_periph_clock_source(periph_id, parent, &mux_bits,
&divider_bits);
clock_ll_set_source_bits(periph_id, mux_bits, source);
}
}
static void set_avp_clock_source(u32 src)
......
arch/arm/mach-tegra/tegra114/clock.c
浏览文件 @ 40e1236a
......@@ -496,6 +496,51 @@ u32 *get_periph_source_reg(enum periph_id periph_id)
return &clkrst->crc_clk_src[internal_id];
}
int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
int *divider_bits, int *type)
{
enum periphc_internal_id internal_id;
if (!clock_periph_id_isvalid(periph_id))
return -1;
internal_id = periph_id_to_internal_id[periph_id];
if (!periphc_internal_id_isvalid(internal_id))
return -1;
*type = clock_periph_type[internal_id];
if (!clock_type_id_isvalid(*type))
return -1;
*mux_bits = clock_source[*type][CLOCK_MAX_MUX];
if (*type == CLOCK_TYPE_PCMT16)
*divider_bits = 16;
else
*divider_bits = 8;
return 0;
}
enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
{
enum periphc_internal_id internal_id;
int type;
if (!clock_periph_id_isvalid(periph_id))
return CLOCK_ID_NONE;
internal_id = periph_id_to_internal_id[periph_id];
if (!periphc_internal_id_isvalid(internal_id))
return CLOCK_ID_NONE;
type = clock_periph_type[internal_id];
if (!clock_type_id_isvalid(type))
return CLOCK_ID_NONE;
return clock_source[type][source];
}
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
......@@ -512,23 +557,10 @@ int get_periph_clock_source(enum periph_id periph_id,
enum clock_id parent, int *mux_bits, int *divider_bits)
{
enum clock_type_id type;
enum periphc_internal_id internal_id;
int mux;
assert(clock_periph_id_isvalid(periph_id));
internal_id = periph_id_to_internal_id[periph_id];
assert(periphc_internal_id_isvalid(internal_id));
type = clock_periph_type[internal_id];
assert(clock_type_id_isvalid(type));
int mux, err;
*mux_bits = clock_source[type][CLOCK_MAX_MUX];
if (type == CLOCK_TYPE_PCMT16)
*divider_bits = 16;
else
*divider_bits = 8;
err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
assert(!err);
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
if (clock_source[type][mux] == parent)
......@@ -699,3 +731,26 @@ void arch_timer_init(void)
writel(val, &sysctr->cntcr);
debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
}
struct periph_clk_init periph_clk_init_table[] = {
{ PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
{ PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
{ PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
{ -1, },
};
arch/arm/mach-tegra/tegra124/clock.c
浏览文件 @ 40e1236a
......@@ -642,6 +642,51 @@ u32 *get_periph_source_reg(enum periph_id periph_id)
}
}
int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
int *divider_bits, int *type)
{
enum periphc_internal_id internal_id;
if (!clock_periph_id_isvalid(periph_id))
return -1;
internal_id = periph_id_to_internal_id[periph_id];
if (!periphc_internal_id_isvalid(internal_id))
return -1;
*type = clock_periph_type[internal_id];
if (!clock_type_id_isvalid(*type))
return -1;
*mux_bits = clock_source[*type][CLOCK_MAX_MUX];
if (*type == CLOCK_TYPE_PC2CC3M_T16)
*divider_bits = 16;
else
*divider_bits = 8;
return 0;
}
enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
{
enum periphc_internal_id internal_id;
int type;
if (!clock_periph_id_isvalid(periph_id))
return CLOCK_ID_NONE;
internal_id = periph_id_to_internal_id[periph_id];
if (!periphc_internal_id_isvalid(internal_id))
return CLOCK_ID_NONE;
type = clock_periph_type[internal_id];
if (!clock_type_id_isvalid(type))
return CLOCK_ID_NONE;
return clock_source[type][source];
}
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
......@@ -658,23 +703,10 @@ int get_periph_clock_source(enum periph_id periph_id,
enum clock_id parent, int *mux_bits, int *divider_bits)
{
enum clock_type_id type;
enum periphc_internal_id internal_id;
int mux;
int mux, err;
assert(clock_periph_id_isvalid(periph_id));
internal_id = periph_id_to_internal_id[periph_id];
assert(periphc_internal_id_isvalid(internal_id));
type = clock_periph_type[internal_id];
assert(clock_type_id_isvalid(type));
*mux_bits = clock_source[type][CLOCK_MAX_MUX];
if (type == CLOCK_TYPE_PC2CC3M_T16)
*divider_bits = 16;
else
*divider_bits = 8;
err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
assert(!err);
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
if (clock_source[type][mux] == parent)
......@@ -1107,3 +1139,26 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
return NULL;
}
struct periph_clk_init periph_clk_init_table[] = {
{ PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
{ PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C6, CLOCK_ID_PERIPH },
{ -1, },
};
arch/arm/mach-tegra/tegra186/Makefile
浏览文件 @ 40e1236a
......@@ -3,5 +3,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += ../board186.o
obj-y += cache.o
obj-y += nvtboot_ll.o
obj-y += nvtboot_mem.o
arch/arm/mach-tegra/tegra186/cache.c 0 → 100644
浏览文件 @ 40e1236a
/*
* Copyright (c) 2016, NVIDIA CORPORATION.
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <asm/system.h>
#define SMC_SIP_INVOKE_MCE 0x82FFFF00
#define MCE_SMC_ROC_FLUSH_CACHE 11
int __asm_flush_l3_cache(void)
{
struct pt_regs regs = {0};
isb();
regs.regs[0] = SMC_SIP_INVOKE_MCE | MCE_SMC_ROC_FLUSH_CACHE;
smc_call(&regs);
return 0;
}
arch/arm/mach-tegra/tegra20/clock.c
浏览文件 @ 40e1236a
......@@ -413,46 +413,78 @@ u32 *get_periph_source_reg(enum periph_id periph_id)
return &clkrst->crc_clk_src[internal_id];
}
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
*
* There is special code here to handle the one source type with 5 sources.
*
* @param periph_id peripheral to start
* @param source PLL id of required parent clock
* @param mux_bits Set to number of bits in mux register: 2 or 4
* @param divider_bits Set to number of divider bits (8 or 16)
* @return mux value (0-4, or -1 if not found)
*/
int get_periph_clock_source(enum periph_id periph_id,
enum clock_id parent, int *mux_bits, int *divider_bits)
int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
int *divider_bits, int *type)
{
enum clock_type_id type;
enum periphc_internal_id internal_id;
int mux;
assert(clock_periph_id_isvalid(periph_id));
if (!clock_periph_id_isvalid(periph_id))
return -1;
internal_id = periph_id_to_internal_id[periph_id];
assert(periphc_internal_id_isvalid(internal_id));
if (!periphc_internal_id_isvalid(internal_id))
return -1;
type = clock_periph_type[internal_id];
assert(clock_type_id_isvalid(type));
*type = clock_periph_type[internal_id];
if (!clock_type_id_isvalid(*type))
return -1;
/*
* Special cases here for the clock with a 4-bit source mux and I2C
* with its 16-bit divisor
*/
if (type == CLOCK_TYPE_PCXTS)
if (*type == CLOCK_TYPE_PCXTS)
*mux_bits = MASK_BITS_31_28;
else
*mux_bits = MASK_BITS_31_30;
if (type == CLOCK_TYPE_PCMT16)
if (*type == CLOCK_TYPE_PCMT16)
*divider_bits = 16;
else
*divider_bits = 8;
return 0;
}
enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
{
enum periphc_internal_id internal_id;
int type;
if (!clock_periph_id_isvalid(periph_id))
return CLOCK_ID_NONE;
internal_id = periph_id_to_internal_id[periph_id];
if (!periphc_internal_id_isvalid(internal_id))
return CLOCK_ID_NONE;
type = clock_periph_type[internal_id];
if (!clock_type_id_isvalid(type))
return CLOCK_ID_NONE;
return clock_source[type][source];
}
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
*
* There is special code here to handle the one source type with 5 sources.
*
* @param periph_id peripheral to start
* @param source PLL id of required parent clock
* @param mux_bits Set to number of bits in mux register: 2 or 4
* @param divider_bits Set to number of divider bits (8 or 16)
* @return mux value (0-4, or -1 if not found)
*/
int get_periph_clock_source(enum periph_id periph_id,
enum clock_id parent, int *mux_bits, int *divider_bits)
{
enum clock_type_id type;
int mux, err;
err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
assert(!err);
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
if (clock_source[type][mux] == parent)
return mux;
......@@ -717,3 +749,24 @@ int tegra_plle_enable(void)
return 0;
}
struct periph_clk_init periph_clk_init_table[] = {
{ PERIPH_ID_SPI1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
{ PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
{ PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
{ PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
{ -1, },
};
arch/arm/mach-tegra/tegra210/clock.c
浏览文件 @ 40e1236a
......@@ -732,6 +732,51 @@ u32 *get_periph_source_reg(enum periph_id periph_id)
return &clkrst->crc_clk_src_y[internal_id];
}
int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
int *divider_bits, int *type)
{
enum periphc_internal_id internal_id;
if (!clock_periph_id_isvalid(periph_id))
return -1;
internal_id = periph_id_to_internal_id[periph_id];
if (!periphc_internal_id_isvalid(internal_id))
return -1;
*type = clock_periph_type[internal_id];
if (!clock_type_id_isvalid(*type))
return -1;
*mux_bits = clock_source[*type][CLOCK_MAX_MUX];
if (*type == CLOCK_TYPE_PC2CC3M_T16)
*divider_bits = 16;
else
*divider_bits = 8;
return 0;
}
enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
{
enum periphc_internal_id internal_id;
int type;
if (!clock_periph_id_isvalid(periph_id))
return CLOCK_ID_NONE;
internal_id = periph_id_to_internal_id[periph_id];
if (!periphc_internal_id_isvalid(internal_id))
return CLOCK_ID_NONE;
type = clock_periph_type[internal_id];
if (!clock_type_id_isvalid(type))
return CLOCK_ID_NONE;
return clock_source[type][source];
}
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
......@@ -748,23 +793,10 @@ int get_periph_clock_source(enum periph_id periph_id,
enum clock_id parent, int *mux_bits, int *divider_bits)
{
enum clock_type_id type;
enum periphc_internal_id internal_id;
int mux;
assert(clock_periph_id_isvalid(periph_id));
internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
assert(periphc_internal_id_isvalid(internal_id));
type = clock_periph_type[internal_id];
assert(clock_type_id_isvalid(type));
int mux, err;
*mux_bits = clock_source[type][CLOCK_MAX_MUX];
if (type == CLOCK_TYPE_PC2CC3M_T16)
*divider_bits = 16;
else
*divider_bits = 8;
err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
assert(!err);
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
if (clock_source[type][mux] == parent)
......@@ -1225,3 +1257,26 @@ int tegra_plle_enable(void)
return 0;
}
struct periph_clk_init periph_clk_init_table[] = {
{ PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
{ PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C6, CLOCK_ID_PERIPH },
{ -1, },
};
arch/arm/mach-tegra/tegra30/clock.c
浏览文件 @ 40e1236a
......@@ -476,6 +476,51 @@ u32 *get_periph_source_reg(enum periph_id periph_id)
return &clkrst->crc_clk_src[internal_id];
}
int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
int *divider_bits, int *type)
{
enum periphc_internal_id internal_id;
if (!clock_periph_id_isvalid(periph_id))
return -1;
internal_id = periph_id_to_internal_id[periph_id];
if (!periphc_internal_id_isvalid(internal_id))
return -1;
*type = clock_periph_type[internal_id];
if (!clock_type_id_isvalid(*type))
return -1;
*mux_bits = clock_source[*type][CLOCK_MAX_MUX];
if (*type == CLOCK_TYPE_PCMT16)
*divider_bits = 16;
else
*divider_bits = 8;
return 0;
}
enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
{
enum periphc_internal_id internal_id;
int type;
if (!clock_periph_id_isvalid(periph_id))
return CLOCK_ID_NONE;
internal_id = periph_id_to_internal_id[periph_id];
if (!periphc_internal_id_isvalid(internal_id))
return CLOCK_ID_NONE;
type = clock_periph_type[internal_id];
if (!clock_type_id_isvalid(type))
return CLOCK_ID_NONE;
return clock_source[type][source];
}
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
......@@ -492,23 +537,10 @@ int get_periph_clock_source(enum periph_id periph_id,
enum clock_id parent, int *mux_bits, int *divider_bits)
{
enum clock_type_id type;
enum periphc_internal_id internal_id;
int mux;
int mux, err;
assert(clock_periph_id_isvalid(periph_id));
internal_id = periph_id_to_internal_id[periph_id];
assert(periphc_internal_id_isvalid(internal_id));
type = clock_periph_type[internal_id];
assert(clock_type_id_isvalid(type));
*mux_bits = clock_source[type][CLOCK_MAX_MUX];
if (type == CLOCK_TYPE_PCMT16)
*divider_bits = 16;
else
*divider_bits = 8;
err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
assert(!err);
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
if (clock_source[type][mux] == parent)
......@@ -763,3 +795,26 @@ int tegra_plle_enable(void)
return 0;
}
struct periph_clk_init periph_clk_init_table[] = {
{ PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
{ PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
{ PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
{ PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
{ -1, },
};
board/nvidia/seaboard/seaboard.c
浏览文件 @ 40e1236a
......@@ -44,6 +44,12 @@ void pin_mux_mmc(void)
void pin_mux_usb(void)
{
/* For USB's GPIO PD0. For now, since we have no pinmux in fdt */
/* For USB0's GPIO PD0. For now, since we have no pinmux in fdt */
pinmux_tristate_disable(PMUX_PINGRP_SLXK);
/* For USB1's ULPI signals */
funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
/* USB1 PHY reset GPIO */
pinmux_tristate_disable(PMUX_PINGRP_UAC);
}
configs/seaboard_defconfig
浏览文件 @ 40e1236a
......@@ -35,6 +35,8 @@ CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
configs/ventana_defconfig
浏览文件 @ 40e1236a
......@@ -34,6 +34,8 @@ CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
drivers/clk/tegra/Kconfig
浏览文件 @ 40e1236a
config TEGRA_CAR_CLOCK
bool "Enable Tegra CAR-based clock driver"
depends on TEGRA_CAR
help
Enable support for manipulating Tegra's on-SoC clocks via direct
register access to the Tegra CAR (Clock And Reset controller).
config TEGRA186_CLOCK
bool "Enable Tegra186 BPMP-based clock driver"
depends on TEGRA186_BPMP
......
drivers/clk/tegra/Makefile
浏览文件 @ 40e1236a
......@@ -2,4 +2,5 @@
#
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_TEGRA_CAR_CLOCK) += tegra-car-clk.o
obj-$(CONFIG_TEGRA186_CLOCK) += tegra186-clk.o
drivers/clk/tegra/tegra-car-clk.c 0 → 100644
浏览文件 @ 40e1236a
/*
* Copyright (c) 2016, NVIDIA CORPORATION.
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
static int tegra_car_clk_request(struct clk *clk)
{
debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
clk->id);
/*
* Note that the first PERIPH_ID_COUNT clock IDs (where the value
* varies per SoC) are the peripheral clocks, which use a numbering
* scheme that matches HW registers 1:1. There are other clock IDs
* beyond this that are assigned arbitrarily by the Tegra CAR DT
* binding. Due to the implementation of this driver, it currently
* only supports the peripheral IDs.
*/
if (clk->id >= PERIPH_ID_COUNT)
return -EINVAL;
return 0;
}
static int tegra_car_clk_free(struct clk *clk)
{
debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
clk->id);
return 0;
}
static ulong tegra_car_clk_get_rate(struct clk *clk)
{
enum clock_id parent;
debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
clk->id);
parent = clock_get_periph_parent(clk->id);
return clock_get_periph_rate(clk->id, parent);
}
static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
{
enum clock_id parent;
debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
clk->dev, clk->id);
parent = clock_get_periph_parent(clk->id);
return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
}
static int tegra_car_clk_enable(struct clk *clk)
{
debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
clk->id);
clock_enable(clk->id);
return 0;
}
static int tegra_car_clk_disable(struct clk *clk)
{
debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
clk->id);
clock_disable(clk->id);
return 0;
}
static struct clk_ops tegra_car_clk_ops = {
.request = tegra_car_clk_request,
.free = tegra_car_clk_free,
.get_rate = tegra_car_clk_get_rate,
.set_rate = tegra_car_clk_set_rate,
.enable = tegra_car_clk_enable,
.disable = tegra_car_clk_disable,
};
static int tegra_car_clk_probe(struct udevice *dev)
{
debug("%s(dev=%p)\n", __func__, dev);
return 0;
}
U_BOOT_DRIVER(tegra_car_clk) = {
.name = "tegra_car_clk",
.id = UCLASS_CLK,
.probe = tegra_car_clk_probe,
.ops = &tegra_car_clk_ops,
};
drivers/i2c/tegra_i2c.c
浏览文件 @ 40e1236a
......@@ -12,27 +12,15 @@
#include <fdtdec.h>
#include <i2c.h>
#include <asm/io.h>
#ifdef CONFIG_TEGRA186
#include <clk.h>
#include <reset.h>
#else
#ifndef CONFIG_TEGRA186
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/clk_rst.h>
#endif
#include <asm/arch/gpio.h>
#include <asm/arch-tegra/tegra_i2c.h>
/*
* FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
* should not be present. These are needed because newer Tegra SoCs support
* only the standard clock/reset APIs, whereas older Tegra SoCs support only
* a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
* fixed to implement the standard APIs, and all drivers converted to solely
* use the new standard APIs, with no ifdefs.
*/
DECLARE_GLOBAL_DATA_PTR;
enum i2c_type {
......@@ -44,12 +32,8 @@ enum i2c_type {
/* Information about i2c controller */
struct i2c_bus {
int id;
#ifdef CONFIG_TEGRA186
struct reset_ctl reset_ctl;
struct clk clk;
#else
enum periph_id periph_id;
#endif
int speed;
int pinmux_config;
struct i2c_control *control;
......@@ -81,20 +65,15 @@ static void set_packet_mode(struct i2c_bus *i2c_bus)
static void i2c_reset_controller(struct i2c_bus *i2c_bus)
{
/* Reset I2C controller. */
#ifdef CONFIG_TEGRA186
reset_assert(&i2c_bus->reset_ctl);
udelay(1);
reset_deassert(&i2c_bus->reset_ctl);
udelay(1);
#else
reset_periph(i2c_bus->periph_id, 1);
#endif
/* re-program config register to packet mode */
set_packet_mode(i2c_bus);
}
#ifdef CONFIG_TEGRA186
static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
{
int ret;
......@@ -114,7 +93,6 @@ static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
return 0;
}
#endif
static void i2c_init_controller(struct i2c_bus *i2c_bus)
{
......@@ -126,12 +104,7 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus)
* here, in section 23.3.1, but in fact we seem to need a factor of
* 16 to get the right frequency.
*/
#ifdef CONFIG_TEGRA186
i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8);
#else
clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
i2c_bus->speed * 2 * 8);
#endif
if (i2c_bus->type == TYPE_114) {
/*
......@@ -151,12 +124,7 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus)
debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
clk_div_stdfst_mode);
#ifdef CONFIG_TEGRA186
i2c_init_clock(i2c_bus, rate);
#else
clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
rate);
#endif
}
/* Reset I2C controller. */
......@@ -170,7 +138,7 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus)
}
#ifndef CONFIG_TEGRA186
funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config);
funcmux_select(i2c_bus->clk.id, i2c_bus->pinmux_config);
#endif
}
......@@ -392,23 +360,13 @@ static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
static int tegra_i2c_probe(struct udevice *dev)
{
struct i2c_bus *i2c_bus = dev_get_priv(dev);
#ifdef CONFIG_TEGRA186
int ret;
#else
const void *blob = gd->fdt_blob;
int node = dev->of_offset;
#endif
bool is_dvc;
i2c_bus->id = dev->seq;
i2c_bus->type = dev_get_driver_data(dev);
i2c_bus->regs = (struct i2c_ctlr *)dev_get_addr(dev);
/*
* We don't have a binding for pinmux yet. Leave it out for now. So
* far no one needs anything other than the default.
*/
#ifdef CONFIG_TEGRA186
ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
if (ret) {
error("reset_get_by_name() failed: %d\n", ret);
......@@ -419,9 +377,13 @@ static int tegra_i2c_probe(struct udevice *dev)
error("clk_get_by_name() failed: %d\n", ret);
return ret;
}
#else
#ifndef CONFIG_TEGRA186
/*
* We don't have a binding for pinmux yet. Leave it out for now. So
* far no one needs anything other than the default.
*/
i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
i2c_bus->periph_id = clock_decode_periph_id(blob, node);
/*
* We can't specify the pinmux config in the fdt, so I2C2 will not
......@@ -429,11 +391,9 @@ static int tegra_i2c_probe(struct udevice *dev)
* You could add in this little hack if you need to use it.
* The correct solution is a pinmux binding in the fdt.
*
* if (i2c_bus->periph_id == PERIPH_ID_I2C2)
* if (i2c_bus->clk.id == PERIPH_ID_I2C2)
* i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
*/
if (i2c_bus->periph_id == -1)
return -EINVAL;
#endif
is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
......@@ -444,14 +404,8 @@ static int tegra_i2c_probe(struct udevice *dev)
i2c_bus->control = &i2c_bus->regs->control;
}
i2c_init_controller(i2c_bus);
debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs,
#ifndef CONFIG_TEGRA186
i2c_bus->periph_id,
#else
-1,
#endif
i2c_bus->speed);
debug("%s: controller bus %d at %p, speed %d: ",
is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, i2c_bus->speed);
return 0;
}
......
drivers/misc/Kconfig
浏览文件 @ 40e1236a
......@@ -129,6 +129,13 @@ config PCA9551_I2C_ADDR
help
The I2C address of the PCA9551 LED controller.
config TEGRA_CAR
bool "Enable support for the Tegra CAR driver"
depends on TEGRA_NO_BPMP
help
The Tegra CAR (Clock and Reset Controller) is a HW module that
controls almost all clocks and resets in a Tegra SoC.
config TEGRA186_BPMP
bool "Enable support for the Tegra186 BPMP driver"
depends on TEGRA186
......
drivers/misc/Makefile
浏览文件 @ 40e1236a
......@@ -42,6 +42,7 @@ obj-$(CONFIG_SANDBOX) += spltest_sandbox.o
endif
endif
obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
obj-$(CONFIG_TEGRA_CAR) += tegra_car.o
obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
......
drivers/misc/tegra_car.c 0 → 100644
浏览文件 @ 40e1236a
/*
* Copyright (c) 2016, NVIDIA CORPORATION.
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <dm.h>
#include <dm/lists.h>
#include <dm/root.h>
/**
* The CAR exposes multiple different services. We create a sub-device for
* each separate type of service, since each device must be of the appropriate
* UCLASS.
*/
static int tegra_car_bpmp_bind(struct udevice *dev)
{
int ret;
struct udevice *child;
debug("%s(dev=%p)\n", __func__, dev);
ret = device_bind_driver_to_node(dev, "tegra_car_clk", "tegra_car_clk",
dev->of_offset, &child);
if (ret)
return ret;
ret = device_bind_driver_to_node(dev, "tegra_car_reset",
"tegra_car_reset", dev->of_offset,
&child);
if (ret)
return ret;
return 0;
}
static int tegra_car_bpmp_probe(struct udevice *dev)
{
debug("%s(dev=%p)\n", __func__, dev);
return 0;
}
static int tegra_car_bpmp_remove(struct udevice *dev)
{
debug("%s(dev=%p)\n", __func__, dev);
return 0;
}
static const struct udevice_id tegra_car_bpmp_ids[] = {
{ .compatible = "nvidia,tegra20-car" },
{ .compatible = "nvidia,tegra30-car" },
{ .compatible = "nvidia,tegra114-car" },
{ .compatible = "nvidia,tegra124-car" },
{ .compatible = "nvidia,tegra210-car" },
{ }
};
U_BOOT_DRIVER(tegra_car_bpmp) = {
.name = "tegra_car",
.id = UCLASS_MISC,
.of_match = tegra_car_bpmp_ids,
.bind = tegra_car_bpmp_bind,
.probe = tegra_car_bpmp_probe,
.remove = tegra_car_bpmp_remove,
};
drivers/mmc/tegra_mmc.c
浏览文件 @ 40e1236a
此差异已折叠。
drivers/reset/Kconfig
浏览文件 @ 40e1236a
......@@ -20,6 +20,13 @@ config SANDBOX_RESET
simply accepts requests to reset various HW modules without actually
doing anything beyond a little error checking.
config TEGRA_CAR_RESET
bool "Enable Tegra CAR-based reset driver"
depends on TEGRA_CAR
help
Enable support for manipulating Tegra's on-SoC reset signals via
direct register access to the Tegra CAR (Clock And Reset controller).
config TEGRA186_RESET
bool "Enable Tegra186 BPMP-based reset driver"
depends on TEGRA186_BPMP
......
drivers/reset/Makefile
浏览文件 @ 40e1236a
......@@ -5,4 +5,5 @@
obj-$(CONFIG_DM_RESET) += reset-uclass.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
drivers/reset/tegra-car-reset.c 0 → 100644
浏览文件 @ 40e1236a
此差异已折叠。
drivers/usb/host/ehci-tegra.c
浏览文件 @ 40e1236a
......@@ -600,9 +600,18 @@ static int init_ulpi_usb_controller(struct fdt_usb *config,
/* reset ULPI phy */
if (dm_gpio_is_valid(&config->phy_reset_gpio)) {
dm_gpio_set_value(&config->phy_reset_gpio, 0);
mdelay(5);
/*
* This GPIO is typically active-low, and marked as such in
* device tree. dm_gpio_set_value() takes this into account
* and inverts the value we pass here if required. In other
* words, this first call logically asserts the reset signal,
* which typically results in driving the physical GPIO low,
* and the second call logically de-asserts the reset signal,
* which typically results in driver the GPIO high.
*/
dm_gpio_set_value(&config->phy_reset_gpio, 1);
mdelay(5);
dm_gpio_set_value(&config->phy_reset_gpio, 0);
}
/* Reset the usb controller */
......
include/configs/tegra-common.h
浏览文件 @ 40e1236a
......@@ -76,11 +76,12 @@
* Increasing the size of the IO buffer as default nfsargs size is more
* than 256 and so it is not possible to edit it
*/
#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
......
include/dt-bindings/clock/tegra30-car.h
浏览文件 @ 40e1236a
......@@ -92,7 +92,7 @@
#define TEGRA30_CLK_OWR 71
#define TEGRA30_CLK_AFI 72
#define TEGRA30_CLK_CSITE 73
#define TEGRA30_CLK_PCIEX 74
/* 74 */
#define TEGRA30_CLK_AVPUCQ 75
#define TEGRA30_CLK_LA 76
/* 77 */
......
include/dt-bindings/memory/tegra114-mc.h 0 → 100644
浏览文件 @ 40e1236a
此差异已折叠。
include/dt-bindings/memory/tegra210-mc.h 0 → 100644
浏览文件 @ 40e1236a
此差异已折叠。
include/dt-bindings/memory/tegra30-mc.h 0 → 100644
浏览文件 @ 40e1236a
此差异已折叠。
include/dt-bindings/thermal/tegra124-soctherm.h
浏览文件 @ 40e1236a
......@@ -9,5 +9,6 @@
#define TEGRA124_SOCTHERM_SENSOR_MEM 1
#define TEGRA124_SOCTHERM_SENSOR_GPU 2
#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
#define TEGRA124_SOCTHERM_SENSOR_NUM 4
#endif
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