- 05 11月, 2019 33 次提交
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由 Peng Fan 提交于
add phy-reset-gpios to reset phy Add board_phy_config to configure phy Enable DM_ETH Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add more clks for fec_mxc according to Linux Kernel 5.4.0-rc1 drivers/net/ethernet/freescale/fec_main.c. Since i.MX8MQ not support CLK_CCF, so add a check to restrict the code only effect when CONFIG_IMX8M and CONFIG_CLK_CCF both defined. Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Make FEC driver could be used by i.MX8M when CONFIG_FEC_MXC defined in defconfig. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de> Tested-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
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由 Peng Fan 提交于
Drop assigned clocks for clk node, this will break boot on i.MX8MM EVK board. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add set_parent callback, then assigned-clock-parents in dts could be work. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de> Tested-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
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由 Peng Fan 提交于
Add enet ref/timer/PHY_REF/root clk which are required to make enet function well. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de> Tested-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
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由 Peng Fan 提交于
When CONFIG_$(SPL_)CLK not defined, the clock controller device not exist, so to avoid boot failure for platform not have CONFIG_$(SPL_)CLK, add a check. Reviewed-by: NPatrick Wildt <patrick@blueri.se> Tested-by: NPatrick Wildt <patrick@blueri.se> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Support pinctrl/clk/sdhc, include ddr4 timing data. Log: U-Boot SPL 2019.10-rc3-00356-g497c500423-dirty (Sep 16 2019 - 10:54:58 +0800) Normal Boot Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 U-Boot 2019.10-rc3-00356-g497c500423-dirty (Sep 16 2019 - 10:54:58 +0800) CPU: Freescale i.MX8MNano rev1.0 at 24 MHz Reset cause: POR Model: NXP i.MX8MNano DDR4 EVK board DRAM: 2 GiB MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add dtsi for i.MX8MN Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add cfg file for i.MX8MN DDR4 Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add i.MX8MM ccf driver support. Modifed from Linux Kernel 5.3.0-rc1, drop some entries that not used in U-Boot and adapt to U-Boot CCF style. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Cc: Lukasz Majewski <lukma@denx.de>
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由 Peng Fan 提交于
some boards use ddr4, not lpddr4, so we need to check ddr4 firmware. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Support i.MX8MN in imx8m pinctrl driver Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
The IVT offset is changed on i.MX8MN. Use ROM_VERSION to pass the v1 or v2 to mkimage. v1 is for iMX8MQ and iMX8MM v2 is for iMX8M Nano (iMX8MN) Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
No ROM INFO structure on iMX8MN, use new ROM API to get boot device from ROM. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
i.MX8MN has its own get_boot_device, so restrict with i.MX8MQ and i.MX8MM. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
i.MX8MN support loading images with rom api, so we implement reuse board_return_to_bootrom to let ROM loading images. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
i.MX8MN follow same logic as i.MX8MM, so use spl_board_boot_device Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add pin header for i.MX8MN Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
i.MX8MN does not have LVTTL, it has a PE property Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors with TZC380 enabled. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
i.MX8MN has similar architecture with i.MX8MM, so it could reuse the clock code of i.MX8MM, but i.MX8MN has different CCM root configurations, so need a separate root entry. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add a dummy cpu type and support get_cpu_rev for i.MX8MN Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add i.MX8MN kconfig entry Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
The power domain tree is not accepted by Linux Kernel upstream. only a single pd node is used currently, as following: pd: imx8qx-pd { compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; #power-domain-cells = <1>; }; So to migrate to use upstream linux dts, we also need a driver to support this. This patch is to support the new method, compared with legacy power domain tree, it will be simpiler, because each device will has resource id as power domain index, it will be directly passed to scfw, and no need to let power domain build that tree. If multiple power domain is needed, it is the dts node should has correctly power domains entry added and sequence correct. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
The current i.MX8 power domain driver is based on i.MX vendor power domain tree which will retire later. The Linux upstream use a single pd node for power domain driver, and U-Boot will adopt that. When U-Boot i.MX8 dts synced with Linux Kernel upstream and related driver ready, the legacy driver will be removed. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
clk and pinctrl will be get(probed) during each device probe, we don't need to probe them in scu driver. Only need to bind the sub-nodes (clk and iomuxc) of MU node with their drivers. So drop the code to probe the clk/pinctrl, and this patch will make it easy to add more subnodes. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
lpuart0 is the uart used by SPL and U-Boot proper, and DM_SERIAL is enabled. Since uclass power domain is also enabled, to make lpuart work properly, need add u-boot,dm-spl for lpuart power domain and its parent. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
lpuart0 is the uart used by SPL and U-Boot proper, and DM_SERIAL is enabled. Since uclass power domain is also enabled, to make lpuart work properly, need add u-boot,dm-spl for lpuart power domain and its parent. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
with u-boot,dm-spl added for imx8qm-pm node, and SPL_SIMPLE_BUS enabled, the bind and probe code in board file could be removed. Also we need to enlarge SYS_MALLOC_F_LEN to avoid calloc fail. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx由 Tom Rini 提交于
u-boot-imx-20191104 ------------------- - i.MX NAND: nandbcb support for MX6UL / i.MX7 - i.MX8: support for HAB - Convert to DM (opos6ul, mccmon6) - Toradex i.MX6ull colibri - sync DTS with kernel Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/606853416
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由 Tom Rini 提交于
- Various CPSW related improvements, DTS resync
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由 Grygorii Strashko 提交于
Conver TI CPSW driver to use dev/ofnode api. Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> [trini: Add <dm/ofnode.h> to provide the prototype to ofnode] Signed-off-by: NTom Rini <trini@konsulko.com>
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- 04 11月, 2019 7 次提交
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https://gitlab.denx.de/u-boot/custodians/u-boot-x86由 Tom Rini 提交于
- Add support for Intel FSP-S and FSP-T in binman - Correct priority selection for image loaders for SPL - Add a size check for TPL - Various small SPL/TPL bug fixes and changes - SPI: Add support for memory-mapped flash
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由 Tom Rini 提交于
We have once again reached a point where this board does not build in some cases with supported toolchains due to reaching a size constraint. To regain some space, disable support for Plan 9 / RTEMS images with the bootm command. Acked-by: NStefano Babic <sbabic@denx.de> Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Igor Opaniuk 提交于
Add subcommand for add writing BCB only, where we provide appropriate offsets for firmware1 and firmware2 and size. Example of usage: > nandbcb bcbonly 0x00180000 0x00080000 0x00200000 Writing 1024 bytes to 0x0: randomizing OK Writing 1024 bytes to 0x20000: randomizing OK Signed-off-by: NIgor Opaniuk <igor.opaniuk@toradex.com> Tested-by: NMax Krummenacher <max.krummenacher@toradex.com> Reviewed-by: NOleksandr Suvorov <oleksandr.suvorov@toradex.com>
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由 Igor Opaniuk 提交于
Move code for writing FCB/DBBT pages to a separate function Signed-off-by: NIgor Opaniuk <igor.opaniuk@toradex.com> Tested-by: NMax Krummenacher <max.krummenacher@toradex.com> Reviewed-by: NOleksandr Suvorov <oleksandr.suvorov@toradex.com>
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由 Igor Opaniuk 提交于
Add support for updating FCB/DBBT on i.MX7: - additional new fields in FCB structure - Leverage hardware BCH/randomizer for writing FCB Signed-off-by: NIgor Opaniuk <igor.opaniuk@toradex.com> Tested-by: NMax Krummenacher <max.krummenacher@toradex.com> Reviewed-by: NOleksandr Suvorov <oleksandr.suvorov@toradex.com>
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由 Igor Opaniuk 提交于
On i.MX7 in a sake of reducing the disturbances caused by a neighboring cells in the FCB page in the NAND chip, a randomizer is enabled when reading the FCB page by ROM bootloader. Add API for setting BCH to specific layout (and restoring it back) used by ROM bootloader to be able to burn it in a proper way to NAND using nandbcb command. Signed-off-by: NIgor Opaniuk <igor.opaniuk@toradex.com> Signed-off-by: NAnti Sullin <anti.sullin@artecdesign.ee> Tested-by: NMax Krummenacher <max.krummenacher@toradex.com> Reviewed-by: NOleksandr Suvorov <oleksandr.suvorov@toradex.com>
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由 Igor Opaniuk 提交于
Extend GPMI Integrated ECC Control Register Description, include additional defines for enabling randomizer function and providing proper randomizer type. For additional details check i.MX7 APR, section 9.6.6.3 GPMI Integrated ECC Control Register Description (GPMI_ECCCTRLn) Signed-off-by: NIgor Opaniuk <igor.opaniuk@toradex.com> Tested-by: NMax Krummenacher <max.krummenacher@toradex.com> Reviewed-by: NOleksandr Suvorov <oleksandr.suvorov@toradex.com>
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