U-boot binary size has been increased from 512KB to 768KB.

So update CONFIG_SYS_MONITOR_LEN to reflect the same.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.

Initialise/create followings required for SPL framework
      - Add spl.c which defines board_init_f, board_init_r
      - update tlb and ddr accordingly
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T1042RDB_PI board does not have QE connector.

So disable CONFIG_QE and CONFIG_U_QE for T1042RDB_PI
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add deep sleep support on T104xRDB platforms.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.

This support of CPLD includes
 - files and register defintion
 - Commands to swtich alternate bank and default bank
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T1040RDB, T1042RDB header files are very similar so merged into new header file T104xRDB.
T104xRDB header file can support both T1040RDB and T1042RDB_PI header.

Patch makes following changes
-Update Boards.cfg file for T1040RDB and T1042RDB_PI
-Add new T104xRDB header file
-Delete T1040RDB, T1042RDB_PI header file
Signed-off-by: NVijay Rai <vijay.rai@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

add CONFIG_QE, CONFIG_U_QE and CONFIG_SYS_QE_FW_ADDR into
"include/configs/T1040RDB.h"
Signed-off-by: NZhao Qiang <B45475@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.
Signed-off-by: NZhao Qiang <B45475@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Update following DDR related settings for T1040RDB, T1042RDB_PI
-Correct number of chip selects to two as t1040 supports
 two Chip selects.
-Update board_specific_parameters udimm structure with settings
 derived via calibration.
-Update ddr_raw_timing sructure corresponding to DIMM.
-Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
 but on T104xRDB, on setting this , DDR instability is observed.
 Board-level debugging is in progress.

Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

This commit removes platform CONFIG_SYS_HZ definition for the
remainders of part1 (commit cdb23792) and part2 (commit f232950f).
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Rob Herring <rob.herring@calxeda.com>

This covers only non-L2 switch ethernet interfaces i.e.
RGMII and SGMII interface for both T1040RDB and T1042RDB_PI

T1040RDB is configured as serdes protocol 0x66 which can
support following interfaces
    2 RGMIIS on DTSEC4, DTSEC5
    1 SGMII on DTSEC3

T1042RDB_PI is configured as serdes protocol 0x06 which can
support following interfaces
    2 RGMIIS on DTSEC4, DTSEC5
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: Minor change in commit message]
Signed-off-by: NYork Sun <yorksun@freescale.com>

Add usb2 node entry in "hwconfig string"

Remove controller interleaving from hwconfig string as T1040
has only one DDR conroller

SPI related macros which were earlier under #ifdef CONFIG_SPIFLASH
are move outside so that they are defined for all cases as these
macros are also used by other u-boot code

Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: Minor change to commit message]
Signed-off-by: NYork Sun <yorksun@freescale.com>

Define CONFIG_MPC85xx in arch/powerpc/cpu/mpc85xx/config.mk
because all target boards with mpc85xx cpu define it.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

u-boot binary size for Freescale mpc85xx platforms is 512KB.
This has been reached to upper limit for some of the platforms causig
linker error.

So, Increase the u-boot binary size to 768KB.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>

The last users of CONFIG_KGDB_SER_INDEX were removed more than 3 years
ago in commits 550650dd and bf16500f, either kgdb subsystem should
care about this parameter or it should be gone completely.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.
Signed-off-by: NYork Sun <yorksun@freescale.com>

T1040RDB is Freescale Reference Design Board supporting
the T1040 QorIQ Power Architecture™ processor.

 T1040RDB board Overview
 -----------------------
 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
    -  Packet parsing, classification, and distribution
    -  Queue management for scheduling, packet sequencing, and congestion
       management
    -  Cryptography Acceleration
    - RegEx Pattern Matching Acceleration
    - IEEE Std 1588 support
    - Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
    - Integrated 8-port Gigabit Ethernet switch
    - Four 1 Gbps Ethernet controllers
 - SERDES Connections, 8 lanes supporting:
    - PCI
    - SGMII
    - QSGMII
    - SATA 2.0
 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
   Interleaving
 -IFC/Local Bus
    - NAND flash: 1GB 8-bit NAND flash
    - NOR: 128MB 16-bit NOR Flash
 - Ethernet
    - Two on-board RGMII 10/100/1G ethernet ports.
    - PHY #0 remains powered up during deep-sleep
 - CPLD
 - Clocks
    - System and DDR clock (SYSCLK, “DDRCLK”)
    - SERDES clocks
 - Power Supplies
 - USB
    - Supports two USB 2.0 ports with integrated PHYs
    - Two type A ports with 5V@1.5A per port.
 - SDHC
    - SDHC/SDXC connector
 - SPI
    - On-board 64MB SPI flash
 - I2C
    - Devices connected: EEPROM, thermal monitor, VID controller
 - Other IO
    - Two Serial ports
    - ProfiBus port
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: fixed Makefile]
Acked-by: NYork Sun <yorksun@freescale.com>

Use a default RCW of protocol 0x66.
A PBI configure file which uses CPC as 256KB SRAM. It can be used by
PBL tool on T1040 to build a pbl boot image.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>

T1040QDS is a high-performance computing evaluation, development and
test platform supporting the T1040 QorIQ Power Architecture™ processor.

 T1040QDS board Overview
 -----------------------
 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
    -  Packet parsing, classification, and distribution
    -  Queue management for scheduling, packet sequencing, and congestion
    	management
    -  Cryptography Acceleration
    - RegEx Pattern Matching Acceleration
    - IEEE Std 1588 support
    - Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
    - Integrated 8-port Gigabit Ethernet switch
    - Four 1 Gbps Ethernet controllers
 - SERDES Connections, 8 lanes supporting:
      — PCI Express: supporting Gen 1 and Gen 2;
      — SGMII
      — QSGMII
      — SATA 2.0
      — Aurora debug with dedicated connectors
 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
   Interleaving
 -IFC/Local Bus
     - NAND flash: 8-bit, async, up to 2GB.
     - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
     - GASIC: Simple (minimal) target within Qixis FPGA
     - PromJET rapid memory download support
 - Ethernet
     - Two on-board RGMII 10/100/1G ethernet ports.
     - PHY #0 remains powered up during deep-sleep
 - QIXIS System Logic FPGA
 - Clocks
     - System and DDR clock (SYSCLK, “DDRCLK”)
     - SERDES clocks
 - Power Supplies
 - Video
     - DIU supports video at up to 1280x1024x32bpp
 - USB
     - Supports two USB 2.0 ports with integrated PHYs
     — Two type A ports with 5V@1.5A per port.
     — Second port can be converted to OTG mini-AB
 - SDHC
     - SDHC port connects directly to an adapter card slot, featuring:
     - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
     — Supporting eMMC memory devices
 - SPI
    -  On-board support of 3 different devices and sizes
 - Other IO
    - Two Serial ports
    - ProfiBus port
    - Four I2C ports
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: fix conflict in boards.cfg]
Acked-by-by: NYork Sun <yorksun@freescale.com>

Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which
uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a
pbl boot image.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>

This patch is for board config file not to add CONFIG_SECURE_BOOT
condition for include the asm/fsl_secure_boot.h.
Signed-off-by: NPo Liu <Po.Liu@freescale.com>

1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860.
2. Decrease RMan liodn offset number.
SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3.
For t4240 and b4860, RMan liodn base is assigned to 922, the original
offset number is too large that the liodn (base+offset 922+678 = 1600)
is greater than 0x500 the maximum liodn number.
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

1) Add support in B4860 board files for using IDT driver where
   IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer
   that generate different refclks for SerDes modules, used this driver
   for reconfiguring SerDes1 Refclks(based on SerDes1 protocols)
   for CPRI to work. CPRI works on 122.88MHz and default refclks coming
   on board are not suitable for it
2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file
   to b4860qds board file, as SerDes1 Refclk1 would come from
   PHY MUX in case of certain protocols, that have been checked here.
   This change would make on board SGMIIs to work
3) Add I2C addresses for IDT8T49N222A devices in board/include file
4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist
Signed-off-by: NShaveta Leekha <shaveta@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>

Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board
specific feature and belongs to SoC header.
Signed-off-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: NTom Rini <trini@ti.com>

- added to fsl_i2c driver new multibus/multiadpater support
- adapted all config files, which uses this driver
Signed-off-by: NHeiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>

Relax parameters to give address latching more time to setup.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

When a b4860qds board boots from SRIO or PCIE, it needs to finish these
processes:
	1. Set all the cores in holdoff status.
	2. Set the boot location to one PCIE or SRIO interface by RCW.
	3. Set a specific TLB entry for the boot process.
	4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
	5. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	6. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	7. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro
"CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature
when building the u-boot image.

You can get some description about this macro in README file, and for more
information about the feature of Boot from SRIO/PCIE, please refer to the
document doc/README.srio-pcie-boot-corenet.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The pci_indirect.c file is always compiled when
CONFIG_PCI is defined although the indirect PCI
bridge support is not needed by every board.

Introduce a new CONFIG_PCI_INDIRECT_BRIDGE
config option and only compile indirect PCI
bridge support if this options is enabled.

Also add the new option into the configuration
files of the boards which needs that.

Compile tested for powerpc, x86, arm and nds32.
MAKEALL results:

powerpc:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 641
  Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB )
  ----------------------------------------------------------
  Note: the warnings for ELPPC and MPC8323ERDB are present even
  without the actual patch.

x86:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 1
  ----------------------------------------------------------

arm:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 311
  ----------------------------------------------------------

nds32:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 3
  ----------------------------------------------------------

Cc: Tom Rini <trini@ti.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>

Signed-off-by: NShaveta Leekha <shaveta@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify
the defines.
- Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere.
- defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G.

Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
	The PHY addresses of Teranetics PHY on XAUI riser card are assigned
	based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
	AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
        and slot2
- Configure MDIO for 10Gig Mac
Signed-off-by: NSuresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor.

B4860QDS Overview
------------------
- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
  ECC, 4 GB of memory in two ranks of 2 GB.
- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,  ECC, 2 GB of memory. Single rank.
- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
  16x16 switch VSC3316
- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
  8x8 switch VSC3308
- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
- B4860 UART port is available over USB-to-UART translator USB2SER or over
  RS232 flat cable.
- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper
  connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA
  connector ports 0 and 2 for AMC mode.
- The B4860 configuration may be loaded from nine bits coded reset
  configuration reset source. The RCW source is set by appropriate
  DIP-switches:
- 16-bit NOR Flash / PROMJet
- QIXIS 8-bit NOR Flash Emulator
- 8-bit NAND Flash
- 24-bit SPI Flash
- Long address I2C EEPROM
- Available debug interfaces are:
	- On-board eCWTAP controller with ETH and USB I/F
	- JTAG/COP 16-pin header for any external TAP controller
	- External JTAG source over AMC to support B2B configuration
	- 70-pin Aurora debug connector
- QIXIS (FPGA) logic:
	- 2 KB internal memory space including
- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
  DDRCLK1, 2 and RTCCLK.
- Two 8T49N222A SerDes ref clock devices support two SerDes port clocks
  - total four refclk, including CPRI clock scheme
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NShaveta Leekha <shaveta@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NSandeep Singh <Sandeep@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Relax parameters to give address latching more time to setup.
Tighten parameters to make it overall faster.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

T4240QDS's QIXIS FPGA has 4k register space size and IFC controller's
Address Mask Registers is initialised 64K size.

So Fix the Address Mask Register initilisation as 4K
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The T4240QDS is a high-performance computing evaluation, development and
test platform supporting the T4240 QorIQ Power Architecture™ processor.

SERDES Connections
  32 lanes grouped into four 8-lane banks
  Two “front side” banks dedicated to Ethernet
  Two “back side” banks dedicated to other protocols
DDR Controllers
  Three independant 64-bit DDR3 controllers
  Supports rates up to 2133 MHz data-rate
  Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
QIXIS System Logic FPGA

Each DDR controller has two DIMM slots. The first slot of each controller
has up to 4 chip selects to support single-, dual- and quad-rank DIMMs.
The second slot has only 2 chip selects to support single- and dual-rank
DIMMs. At any given time, up to total 4 chip selects can be used.

Detail information can be found in doc/README.t4qds
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The P5040 does not have SRIO, so don't put the SRIO definitions in
corenet_ds.h.  They belong in the board-specific header files.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Kill multiple occurances and redeclaration of MK_STR
in favor of __stringify().
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: NTom Rini <trini@ti.com>