- 17 5月, 2014 10 次提交
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由 Prabhakar Kushwaha 提交于
In the earlier patches, the SPL/TPL fraamework was introduced. For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The SPL was loaded by the code from the internal on-chip ROM. The SPL initializes the DDR according to the SPD and loads the final uboot image into DDR, then jump to the DDR to begin execution. For NAND booting way, the nand SPL has size limitation on some board(e.g. P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD and loads the final uboot image into DDR,then jump to the DDR to begin execution. This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL. Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to execute, so the section .resetvec is no longer needed. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
In case of secure boot from NAND, CSPR and FTIM settings are same as non-secure NAND boot. CSPR0 is configured as NAND and CSPR1 is configured as NOR. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 ramneek mehresh 提交于
P1020 SoC which has two USB controllers, but only first one is used on this platform. Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Nikhil Badola 提交于
Define and use CONTROL_REGISTER_W1C_MASK to make sure that w1c bits of usb control register do not get reset while writing any other bit Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com> Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shaveta Leekha 提交于
B4460 differs from B4860 only in number of CPU cores, hence used existing support for B4860. B4460 has 2 PPC cores whereas B4860 has 4 PPC cores. Signed-off-by: NShaveta Leekha <shaveta@freescale.com> Signed-off-by: NSandeep Singh <Sandeep@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Chunhe Lan 提交于
T4160RDB shares the same platform as T4240RDB. T4160 is a low power version of T4240, with the eight e6500 cores, two DDR3 controllers, and same peripheral bus interfaces. Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Chunhe Lan 提交于
By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are mapped to 0xF, which is local memory. But for BSC9132, 0xF is CCSR, 0x0 is local memory. Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Tang Yuantian 提交于
T104xrdb has several sleep management signals that are used for deep sleep. They are enabled by OS to enter deep sleep and should be disabled by u-boot when cores wake up. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ebony Zhu 提交于
According to AN3638, CRC of NXID v1 is at the end of the 256-byte I2C memory. The wrong CRC32 offset prevents Uboot from reading system information from EEPROM. No NXID v0 is being used on Freescale boards. Signed-off-by: NEbony Zhu <b45385@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Chunhe Lan 提交于
This patch adds support for VSC8664 PHY module which can be found on Freescale's T4240RDB boards. Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 14 5月, 2014 2 次提交
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由 Masahiro Yamada 提交于
"make ep8248_config" fails with an error like this: $ make ep8248_config make: *** [ep8248_config] Error 1 Its cause is that there are two entries for "ep8248". The first is around line 652 of boards.cfg. (as Active) The second appears around line 1230. (as Orphan) This bug was accidentally introduced by commit e7e90901. But it is not the author's fault. He just intended to change IDS8247 board. The commiter added ep8248 entry by mistake when he resolved a conflict. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Heiko Schocher <hs@denx.de> Cc: Kim Phillips <kim.phillips@linaro.org> Acked-by: NHeiko Schocher <hs@denx.de> Acked-by: NKim Phillips <kim.phillips@freescale.com>
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- 13 5月, 2014 28 次提交
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由 York Sun 提交于
This patch converts the following boards to use generic board: MPC8536DS, MPC8572DS, MPC8641HPCN, p1_p2_rdb_pc, corenet_ds, t4qds, B4860QDS. It has been tested on NOR boot on MPC8536DS, MPC8572DS, P1021RDB, P4080DS, P5020DS, P5040DS, P3041DS, T4240QDS, B4860QDS. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: Ying Zhang <b40530@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Haijun.Zhang <Haijun.Zhang@freescale.com> CC: Scott Wood <scottwood@freescale.com> CC: Shaohui Xie <Shaohui.Xie@freescale.com>
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由 York Sun 提交于
The argument boot_flag of board_inti_f() hasn't been used for powerpc until recent changing to use generic board. Set it to 0 as a proper value. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
baord_init_f takes one argument, boot_flag. It has not been used for powerpc, until recently changing to use generic board architecture. The boot flag is added as a return value from cpu_init_f(). Signed-off-by: NYork Sun <yorksun@freescale.com> CC: Alexander Graf <agraf@suse.de>
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由 York Sun 提交于
The return value has not been checked by its caller, until recent change of using generic board architecture. The error of this function is not critical enough to hang the system. Printing the warning message is enough to catch user's attention. U-boot should continue to boot to give user a chance to fix the EEPROM. Chaning the return value to 0 to avoid hanging in the board_init_r(). Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
The pointer of device tree comes from r3 for QEMU. This is not the case for normal SoCs out of reset. Having gd->fdt_blob as 0 is important for other functions to detect the non-existence of device tree. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: Alexander Graf <agraf@suse.de>
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由 York Sun 提交于
U-boot image has grown and exceeded the predefined 512KB. Increasing to 768KB to align with other powerpc boards. Tested on MPC8572DS for 32- and 36-bit targets with NOR flash boot. NAND boot is not covered by this patch. Also update board maintainer for these boards. Signed-off-by: NYork Sun <yorksun@freescale.com> Acked-by: NHeiko Schocher <hs@denx.de>
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由 Zhao Qiang 提交于
when qe-ucode fails to be uploaded, "deep sleep" will hang. if there is no qe-ucode, disable qe module for platforms which support "deep sleep" Signed-off-by: NZhao Qiang <B45475@freescale.com>
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由 Alexander Graf 提交于
This patch enables the E500 QEMU board to use the generic cross-arch board infrastructure. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We want to use the TLB mapping helpers in relocated mode as well. These helpers need to have awareness of already occupied TLB entries. We already had them in sync in non-relocated mode, but need to resync them when we move into relocated. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
For the QEMU machine type, we can plug in either e500v2, e500mc, e5500 or e6500 style cores into the system. U-boot has to work with all of them. So avoid using HID1 which is not available on e500mc systems to make sure we don't trap on it. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We only need u-boot to bother about a single core in the QEMU machine. Everything that would require additional knowledge of more cores gets handled by QEMU and passed straight into the payload we execute. Because of this setup, it would be counterproductive to enable SMP support in u-boot. We would have to rip CPUs out of already existing spin tables and respin them from u-boot. It would be a pretty big mess. So only assume we have a single core. This fixes errors about CONFIG_MP being disabled. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Valentin Longchamp 提交于
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
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由 Valentin Longchamp 提交于
This should prevent the problems that the CCF can deadlock with certain traffic patterns. This also fixes the workaround for A-006559 that was not correctly implemented before. Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
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由 Valentin Longchamp 提交于
Fix the IRQ/GPIO settings: all the muxed GPIO/external IRQs that are used as internal interrupts are defined as GPIOs to avoid confusion between the internal/external interrupts. Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
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由 Valentin Longchamp 提交于
This adds the reset support for the following devices that was until then not implemented: - BFTIC4 - QSFPs This also fixes the configuration of the prst behaviour for the other resets: Only the u-boot and kernel relevant subsystems are taken out of reset (pcie, ZL30158, and front eth phy). Most of the prst config move to misc_init_f(), except for the PCIe related ones that are in pci_init_board and the bftic and ZL30158 ones that should be done as soon as possible. Only the behavior of the Hooper reset is changed according to the documentation as the application is not able to not configure the switch when it is not reset. Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
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由 Valentin Longchamp 提交于
This prevents u-boot from accessing into the reserved memory areas that we have for /var and the logbooks. Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
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由 Valentin Longchamp 提交于
This patch defines the post_hotkeys_pressed() function that is used for: - triggering POST memory regions test - starting the test application through the checktestboot command in a script by setting the active bank to testbank The post_hotkeys_pressed return the state of the SELFTEST pin. The patch moves from the complete POST-memory test that is too long in its SLOW version for our production HW test procedure to the much shorter POST-memory-regions test. Finally, the unused #defines for the not so relevant mtest command are removed. Signed-off-by: NStefan Bigler <stefan.bigler@keymile.com> Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
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由 Stefan Bigler 提交于
Add readout of dip-switch to revert to factory settings. If one or more dip-switch are set, launch bank 0 that contains the bootloader to do the required action. Signed-off-by: NStefan Bigler <stefan.bigler@keymile.com> Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
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由 Stefan Bigler 提交于
The unit LEDs are managed by the QRIO CPLD. This patch adds support for accessing these LEDs in the QRIO. The LEDs then are set to a correct boot state: - UNIT-LED is red - BOOT-LED is on. Signed-off-by: NStefan Bigler <stefan.bigler@keymile.com> Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
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由 Shengzhou Liu 提交于
The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
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由 Shengzhou Liu 提交于
Enable errata A006261, A006593, A006379 for T208x. Additionally enable CONFIG_CMD_ERRATA for T2080RDB. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
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由 Shaohui Xie 提交于
Current driver uses a Maximum value for MDIO_HOLD when doing 10G MDIO access, this is due to an errata A-006260 on T4 rev1.0 which is fixed on rev2.0, so remove the maximum value to use the default value for rev2.0. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
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由 Aneesh Bansal 提交于
Secure Boot Target is added for T2080RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
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由 Aneesh Bansal 提交于
T1040RDB.h file is removed and a unified file T104xRDB.h is created. Hence macro CONFIG_T1040 is renamed to CONFIG_T104x. Signed-off-by: NGaurav Kumar Rana <gaurav.rana@freescale.com> Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
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由 Chunhe Lan 提交于
T4240RDB board Specification ---------------------------- Memory subsystem: 6GB DDR3 128MB NOR flash 2GB NAND flash Ethernet: Eight 1G SGMII ports Four 10Gbps SFP+ ports PCIe: Two PCIe slots USB: Two USB2.0 Type A ports SDHC: One SD-card port SATA: One SATA port UART: Dual RJ45 ports Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com> [York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]
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由 Shaveta Leekha 提交于
The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. B4860QDS has a PowerOne ZM7300 programmable digital Power Manager which is programmed as per the value read from the fuses. Reference for this code is taken from t4qds VID implementation. Signed-off-by: NShaveta Leekha <shaveta@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
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由 Shaveta Leekha 提交于
Adds Support for PowerOne ZM7300 voltage regulator. This device is available on some Freescale Boards like B4860QDS and has to be programmed to adjust the voltage on the board. The device is accessible via I2C interface. Signed-off-by: NShaveta Leekha <shaveta@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
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