In current code, we add 1ms dealy after each tuning command for standard
tuning method. Adding this 1ms dealy is because USDHC default check the
CMD CRC and DATA line. If detect the CMD CRC, USDHC standard tuning
IC logic do not wait for the tuning data sending out by the card, trigger
the buffer read ready interrupt immediately, and step to next cycle. So
when next time the new tuning command send out by USDHC, card may still
not send out the tuning data of the upper command，then some eMMC cards
may stuck, can't response to any command, block the whole tuning procedure.

If do not check the CMD CRC for tuning, then do not has this issue. USDHC
will wait for the tuning data of each tuning command and check them. If the
tuning data pass the check, it also means the CMD line also okay for tuning.

So this patch disable the CMD CRC check for tuning, save some time for the
whole tuning procedure.
Signed-off-by: NHaibo Chen <haibo.chen@nxp.com>

Unsupported voltage on voltage switch is not an error, do not
print error message in such a case. This happens e.g. if the
eMMC is already in 1V8 mode or when testing 1V2 mode operation
on systems which only do 3V3/1V8 switching.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

The 3V3/1V8 switching could never have worked on any of the iMXes
ever since 51313b49 ("mmc: fsl_esdhc: support SDR104 and HS200"),
because that commit uses priv->vqmmc_dev when switching voltages on
mode switch, while local vqmmc_dev in probe to store the regulator
pointer. Those are two different variables with the same name. So
the priv->vqmmc_dev was always NULL and thus voltage switch between
modes never really suceeded.

Fix this by assigning priv->vqmmc_dev with value of the vqmmc_dev
in probe.

Fixes: 51313b49 ("mmc: fsl_esdhc: support SDR104 and HS200")
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

Move this uncommon header out of the common header.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Move this uncommon header out of the common header.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Move this header out of the common header.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.

Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.
Signed-off-by: NSimon Glass <sjg@chromium.org>

MMC_LEGACY & SD_LEGACY are not differentiated timings in the spec and
don't have any meaningful differences. Therefore, get rid of all
references to SD_LEGACY and use MMC_LEGACY to mean both of them.
Signed-off-by: NFaiz Abbas <faiz_abbas@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.
Signed-off-by: NSimon Glass <sjg@chromium.org>

At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NAnatolij Gustschin <agust@denx.de>

Drop QorIQ eSDHC specific peripheral clock code.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>

Add compatible "fsl,imxrt-usdhc" to make mmc working on i.MXRT platforms
with CONFIG_DM_MMC=y.
Signed-off-by: NGiulio Benetti <giulio.benetti@benettiengineering.com>

Not all architectures(i.e. i.MXRT) support mxc_get_clock() and use DM_CLK
instead. So building could result in failure due to missing
mxc_get_clock().

Make if(CONFIG_IS_ENABLED(CLK)) an #if statement.
Signed-off-by: NGiulio Benetti <giulio.benetti@benettiengineering.com>

When no GPIO is used to read the card detect status the following
error is seen:

MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... MMC: no card present
*** Warning - No block device, using default environment

Fix it by handling the "broken-cd" property in the same way
that drivers/mmc/sdhci.c does, which considers that the SD card
is present when the "broken-cd" property is passed.

Tested on a imx6ul-evk board.
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Reviewed-by: NStefano Babic <sbabic@denx.de>

At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass
is included in SPL/TPL without any control for boards. Some boards may
want to disable this to reduce code size where GPIOs are not needed in
SPL or TPL.

Add a new Kconfig option to permit this. Default it to 'y' so that
existing boards work correctly.

Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to
preserve the current behaviour. Also update the 74x164 GPIO driver since
it cannot build with SPL.

This allows us to remove the hacks in config_uncmd_spl.h and
Makefile.uncmd_spl (eventually those files should be removed).
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

These functions are CPU-related and do not use driver model. Move them to
cpu_func.h
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

To enable HS400(ES) and UHS for imx8m platforms, update the driver data
to share with imx8qm esdhc_soc_data.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

During mmc initialization, there are several calls to mmc_set_clock
and mmc_set_ios. When mmc_power_off, the mmc->clock will be set,
but the imx driver will use 400KHz. So the following calls
to mmc_set_ios will set the clock several times which is redundant
in fsl_esdhc_imx driver. So let's simplify to remove redundant
clock settings.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Flash system partition with fastboot will earse the partition firstly
The 600ms timeout will fail on some SD Card. Enlarge it to 5s to make
it works for most of sdcard

Cc: guoyin.chen <guoyin.chen@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add i.MX8QM compatible and soc data, the soc data is following Linux
i.MX SDHC driver.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Implement set_enhanced_strobe hook for fsl_esdhc_imx,
,in esdhc_set_timing and esdhc_change_pinstate, also handle HS400_ES.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Use mmc_of_parse to set host_caps.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Should use CONFIG_IS_ENABLED not IS_ENABLED for clock and regulator drivers,
CONFIG_IS_ENABLED will check the CONFIG_SPL_CLK and CONFIG_SPL_DM_REGULATOR
when building SPL.
Signed-off-by: NYe Li <ye.li@nxp.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Dropped useless code for i.MX eSDHC driver.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Tested-by: NSteffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>
Reviewed-by: NMartyn Welch <martyn.welch@collabora.com>
Reviewed-by: NLukasz Majewski <lukma@denx.de>

The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
initially. The later QoriQ series PowerPC processors (which were
evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, and
i.MX series processors were using this driver for their eSDHCs too.

For the two series processors, the eSDHCs are becoming more and
more different. We should have split it into two drivers, like them
(sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel.

This patch is just to create a fsl_esdhc_imx driver which is a copy
of fsl_esdhc driver for i.MX processors. We will convert i.MX processors
to use fsl_esdhc_imx, and clean up the two drivers separately in the
future patches.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Tested-by: NSteffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>
Reviewed-by: NMartyn Welch <martyn.welch@collabora.com>

u-boot is trying to make CONFIG_BLK as a hard requirement
for DM_MMC. But now it's still not.

config BLK
	bool "Support block devices"
	depends on DM
	default y if DM_MMC

When fsl_esdhc driver was reworked for DM_MMC support, DM_MMC
without CONFIG_BLK enabled wasn't considered. This patch is to
fix probe issue without CONFIG_BLK enabled.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: NYinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

PowerPC supports 32 bit address.
So adopt 32 bit addr in fsl_esdhc for CONFIG_PPC.
Signed-off-by: NYinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Signed-off-by: NYinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

This reverts commit 72a89e0d, which
causes the imx53 HSC to hang as the eMMC is not working properly anymore.

The exact error message:
MMC write: dev # 0, block # 2, count 927 ... mmc write failed
0 blocks written: ERROR

imx53 is not using the DDR mode.

Debugging of pre_div and div generation showed that those values are
generated in a way, which is not matching the ones from working setup.

As the original patch was performing code refactoring, let's revert this
change, so all imx53 boards would work again.
Signed-off-by: NLukasz Majewski <lukma@denx.de>

The wp-gpios property is used for gpio, if this is set, the WP pin is muxed
to gpio function, can't be used as internal WP checking. However the codes
remain to use internal WP checking.

This patch changes to examine the "fsl,wp-controller" for enabling internal WP
checking, and "wp-gpios" for muxing to gpio.
Signed-off-by: NYe Li <ye.li@nxp.com>

When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode,
the output clock rate is half of the internal clock rate.

This patch set the DDR_EN bit first for DDR mode, hardware divide
the usdhc clock automatically, then follow the original sdr clock
setting method.
Signed-off-by: NHaibo Chen <haibo.chen@nxp.com>
Signed-off-by: NYe Li <ye.li@nxp.com>

Since the fsl_esdhc will also be used by SPL, make the
preprocessor switches more generic to allow any kind of build.
Signed-off-by: NAbel Vesa <abel.vesa@nxp.com>
Reviewed-by: NFabio Estevam <festevam@gmail.com>
Reviewed-by: NLukasz Majewski <lukma@denx.de>

Add compatible "fsl,imx53-esdhc" to keep mmc working on i.MX53 platforms
with CONFIG_DM_MMC=y
Signed-off-by: NPatrick Bruenn <p.bruenn@beckhoff.com>

This patch has been tested on the mcf54415-based stmark2
board. The eSDHC driver works reliably using DMA mode.
Signed-off-by: NAngelo Dureghello <angelo@sysam.it>

This patch is to make get_cd work well when DM_MMC enabled
Signed-off-by: NYinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The following hang is observed on a Hummingboard 2 MicroSOM
i2eX iMX6D - rev 1.3 with no eMMC populated on board:

U-Boot SPL 2018.11+gf6206f85 (Nov 16 2018 - 00:56:34 +0000)
Trying to boot from MMC1

U-Boot 2018.11+gf6206f85 (Nov 16 2018 - 00:56:34 +0000)

CPU:   Freescale i.MX6D rev1.5 996 MHz (running at 792 MHz)
CPU:   Extended Commercial temperature grade (-20C to 105C) at 33C
Reset cause: POR
Board: MX6 HummingBoard2
DRAM:  1 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment

No panel detected: default to HDMI
Display: HDMI (1024x768)
In:    serial
Out:   serial
Err:   serial
---> hangs

which is caused by the following infinite loop inside esdhc_send_cmd_common()

	while (!(esdhc_read32(&regs->irqstat) & flags))
		;

Instead of looping forever, provide an exit path so that a timeout
error can be propagated in the case irqstat does not report
any interrupts, which may happen when no eMMC is populated on
board.
Reported-by: NRicardo Salveti <rsalveti@rsalveti.net>
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Tested-by: NPeter Robinson <pbrobinson@gmail.com>
Tested-by: NRicardo Salveti <rsalveti@rsalveti.net>

Rename mx8m,MX8M to imx8m,IMX8M
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Signed-off-by: NJon Nettleton <jon@solid-run.com>

When CONIFG_CLK is enabled, use uclass clk api to handle
the clock.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Reviewed-by: NAnatolij Gustschin <agust@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>

Add CONFIG_ARCH_IMX8 to use the 64bits support in usdhc driver.
Signed-off-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Reviewed-by: NAnatolij Gustschin <agust@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>

The strobe dll code is ported from Linux Kernel:
drivers/mmc/host/sdhci-esdhc-imx.c
The comments are from the above file,
"For HS400 eMMC, there is a data_strobe line. This signal is generated
by the device and used for data output and CRC status response output
in HS400 mode. The frequency of this signal follows the frequency of
CLK generated by host. The host receives the data which is aligned to the
edge of data_strobe line. Due to the time delay between CLK line and
data_strobe line, if the delay time is larger than one clock cycle,
then CLK and data_strobe line will be misaligned, read error shows up.
So when the CLK is higher than 100MHz, each clock cycle is short enough,
host should configure the delay target. "
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>