To enable mipi display, we need to enable pmic
rk808 first for lcd3v3 power,which use i2c0 to
communicate with soc. So enable i2c0.
Signed-off-by: NEric Gao <eric.gao@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

when enable PMIC rk808,the system will halt at very
 early stage,log is shown as bellow.

INFO:    plat_rockchip_pmu_init(1211): pd status 3e
INFO:    BL31: Initializing runtime services
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x200000
INFO:    SPSR = 0x3c9
time 44561b, 0 (<<----Just stop here)

It's caused by the absence of "{ }" in syscon_rk3399.c
,which will lead to memory overflow like below.According
 to Sysmap file ,we can find the function buck_get_value
of rk808 is just follow the compatible struct,the pointer
"of_match" point to "buck_get_value",but it is not a
struct and don't have member of compatible, In this case,
system crash. So,on the face, it looks like that rk808 is
guilty.but he is really innocent.

while (of_match->compatible) { <<----------
    if (!strcmp(of_match->compatible, compat)) {
    *of_idp = of_match;
    return 0;
    }
    of_match++;
}
Signed-off-by: NEric Gao <eric.gao@rock-chips.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NKever Yang <kever.yang@rock-chips.com>

The RK3399-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3399.

It provides the following feature set:
 * up to 4GB DDR3
 * on-module SPI-NOR flash
 * on-module eMMC (with 8-bit interace)
 * SD card (on a baseboad) via edge connector
 * Gigabit Ethernet w/ on-module Micrel KSZ9031 GbE PHY
 * HDMI/eDP/MIPI displays
 * 2x MIPI-CSI
 * USB
   - 1x USB 3.0 dual-role (direct connection)
   - 2x USB 3.0 host + 1x USB 2.0 (on-module USB 3.0 hub)
 * on-module STM32 Cortex-M0 companion controller, implementing:
   - low-power RTC functionality (ISL1208 emulation)
   - fan controller (AMC6821 emulation)
   - USB<->CAN bridge controller

Note that we use a multi-payload FIT image for booting and have
Cortex-M0 payload in a separate subimage: we thus rely on the FIT
image loader to put it into the SRAM region that ATF expects it in.
Signed-off-by: NKlaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fixed build warning on puma-rk3399:
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The RK3399-Q7 (Puma) DTS should (of course) be dual-licensed.
This updates the licensing info in the rk3399-puma.dts.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The warm-reset of rk3188 socs keeps the remap setting as it was, so if
it was enabled, the cpu would start from address 0x0 of the sram instead
of address 0x0 of the bootrom, thus making the reset hang.

Therefore make sure the remap is disabled before attempting a warm reset.

Cold reset is not affected by this at all.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NSimon Glass <sjg@chromium.org>

The lower address is reserved for ATF, do not use it.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Most Rockchip socs have the ability to either map the bootrom or a sram
area to the starting address of the cpu by flipping a bit in the GRF.

Newer socs leave this untouched and mapped to the bootrom but the legacy
loaders on rk3188 and before enabled the remap functionality and the
current smp implementation in the Linux kernel also requires it to be
enabled, to bring up secondary cpus.

So to keep smp working in the kernel, mimic the behaviour of the legacy
bootloaders and enable the remap functionality.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NSimon Glass <sjg@chromium.org>

Somehow 43b5c78d ("rockchip: cosmetic: Sort RK3288 boards") moved
the rock board in between some rk3288 board, probably as a result of
rebasing.

So move it back to its original position above all rk3288 boards.

Fixes: 43b5c78d ("rockchip: cosmetic: Sort RK3288 boards")
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NSimon Glass <sjg@chromium.org>

Now that most rockchip SoC based board have usb host support, enable
USB boot targets by default.
Signed-off-by: NEddie Cai <eddie.cai.linux@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Fixed build errors when CONFIG_CMD_USB not defined:
Signed-off-by: NSimon Glass <sjg@chromium.org>

tinker board support ethernet and usb host, so enable USB, PXE and DHCP support.
Signed-off-by: NEddie Cai <eddie.cai.linux@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: NSimon Glass <sjg@chromium.org>

The RK3399 hangs during DMA of the Designware MMC controller, when
performing DMA-based transactions in SPL due to the DDR security settings
left behind by the BootROM (i.e. accesses to the first MB of DRAM are
restricted... however, the DMA is likely to target this first MB, as it
transfers from/to the stack).

System security is not affected, as the final security configuration is
performed by the ATF, which is executed after the SPL stage.

With this fix in place, we can now drop 'fifo-mode' in the DTS for the
RK3399-Q7 (Puma).
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

When writing out some of our results we may now have UTF-8 characters
in there as well.  Translate these to latin-1 and ignore any errors (as
this is for diagnostic and given the githash anything else can be
reconstructed by the user.
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Rini <trini@konsulko.com>

This fixes a regression caused by

commit 07b2b78c
    dm: usb: Convert USB storage to use driver-model for block devs

which caused part_init to be called when it was not previously.
Without this patch, the following happens when a USB sd card reader is used.

=> usb start
starting USB...
USB0:   Port not available.
USB1:   USB EHCI 1.00
scanning bus 1 for devices... 3 USB Device(s) found
       scanning usb for storage devices... Device NOT ready
   Request Sense returned 02 3A 00
 ### ERROR ### Please RESET the board ###

This happens because dev_desc->blksz is 0.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>

We should invalidate the dcache before starting the DMA. In case there are
any dirty lines from the DMA buffer in the cache, subsequent cache-line
replacements may corrupt the buffer in memory while the DMA is still going on.
Cache-line replacement can happen if the CPU tries to bring some other memory
locations into the cache while the DMA is going on.
Signed-off-by: NEddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: NStefan Brüns <stefan.bruens@rwth-aachen.de>

Merely using dma_alloc_coherent does not ensure that there is no stale
data left in the caches for the allocated DMA buffer (i.e. that the
affected cacheline may still be dirty).

The original code was doing the following (on AArch64, which
translates a 'flush' into a 'clean + invalidate'):
  # during initialisation:
      1. allocate buffers via memalign
      	 => buffers may still be modified (cached, dirty)
  # during interrupt processing
      2. clean + invalidate buffers
      	 => may commit stale data from a modified cacheline
      3. read from buffers

This could lead to garbage info being written to buffers before
reading them during even-processing.

To make the event processing more robust, we use the following sequence
for the cache-maintenance:
  # during initialisation:
      1. allocate buffers via memalign
      2. clean + invalidate buffers
      	 (we only need the 'invalidate' part, but dwc3_flush_cache()
	  always performs a 'clean + invalidate')
  # during interrupt processing
      3. read the buffers
      	 (we know these lines are not cached, due to the previous
	  invalidation and no other code touching them in-between)
      4. clean + invalidate buffers
      	 => writes back any modification we may have made during event
	    processing and ensures that the lines are not in the cache
	    the next time we enter interrupt processing

Note that with the original sequence, we observe reproducible
(depending on the cache state: i.e. running dhcp/usb start before will
upset caches to get us around this) issues in the event processing (a
fatal synchronous abort in dwc3_gadget_uboot_handle_interrupt on the
first time interrupt handling is invoked) when running USB mass
storage emulation on our RK3399-Q7 with data-caches on.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

The dwc3_flush_cache() call was declared and used inconsistently:
 * The declaration assumed 'int' for addresses (a potential issue
   when running in a LP64 memory model).
 * The invocation cast the address to 'long'.

This change ensures that both the declaration and usage of this
function consistently uses 'uintptr_t' for correct behaviour even
when the allocated buffers (to be flushed) reside outside of the
lower 32bits of memory.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Both these numbers are calculated in runtime and dynamically assigned
to the device descriptor during bind().
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

We don't want to claim that we support a serial number string and
later return nothing. Because of that, if g_dnl_serial is an empty
string, let's skip setting iSerialNumber to a valid number.
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

A USB String descriptor can be up to 255 characters long and it's not
NULL terminated according to the USB spec. This means our
MAX_STRING_SERIAL should be 256 (to cope with NULL terminator).
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

Some board do not use the dwc2 internal VBUS_DRV signal, but
use a gpio pin to enable the 5.0V VBUS power, add interface to
enable the power in dwc2 driver.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Signed-off-by: NSimon Glass <sjg@chromium.org>

This removes the default environment from the sr1500 header
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

This board has no upstream devicetree in the kernel source,
so set to socfpga_cyclone5_sr1500.dtb.
Signed-off-by: NDalon Westergreen <dwesterg@gmail.com>
Acked-by: NMarek Vasut <marex@denx.de>

--
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE
 - set devicetree name to match socfpga_{fpga model}_{board model}.dts
   pattern

This removes the default environment from the socrates headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

Change default devicetree name to match devicetree name in
upstream kernel source.
Signed-off-by: NDalon Westergreen <dwesterg@gmail.com>
Acked-by: NMarek Vasut <marex@denx.de>

--
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE

This removes the default environment from the SoCKit headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

Change default devicetree name to match devicetree name in
upstream kernel source.
Signed-off-by: NDalon Westergreen <dwesterg@gmail.com>
Acked-by: NMarek Vasut <marex@denx.de>

--
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE

This removes the default environment from the de1 headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

This board does not have a devicetree in the upstream kernel
source so set devicetree to socfpga_cyclone5_de1_soc.dtb.
Signed-off-by: NDalon Westergreen <dwesterg@gmail.com>
Acked-by: NMarek Vasut <marex@denx.de>

--
Changes in V2:
 - Remove unneeded CONFIG_BOOTFILE
 - set devicetree name to match socfpga_{fpga model}_{board model}.dts
   pattern

This removes the default environment from the C5 SoCDK headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

In addition to the above, add support to boot from the custom
a2 type partition.

Change default devicetree name to match devicetree name in
upstream kernel source.
Signed-off-by: NDalon Westergreen <dwesterg@gmail.com>
Acked-by: NMarek Vasut <marex@denx.de>

--
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE

This removes the default environment from the A5 socdk headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

Add support to boot from the custom a2 type partition.

Change default devicetree name to match devicetree name in
upstream kernel source.
Signed-off-by: NDalon Westergreen <dwesterg@gmail.com>
Acked-by: NMarek Vasut <marex@denx.de>

--
Changes in v3:
 - Fix small typo in defconfig, missing "C"
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE
 - Fix dtb name

a5config test
Signed-off-by: NDalon Westergreen <dwesterg@gmail.com>

This removes the default environment from the de0 headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

In addition to the above, add support to boot from the custom
a2 type partition
Signed-off-by: NDalon Westergreen <dwesterg@gmail.com>
Acked-by: NMarek Vasut <marex@denx.de>

--
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE

This adds a common environment and support for distro boot
in the common socfpga header.
Signed-off-by: NDalon Westergreen <dwesterg@gmail.com>
Acked-by: NMarek Vasut <marex@denx.de>

--
Changes in v5:
 - Per Frank, to support OpenSuse the ENV must be after the GPT
Changes in v4:
 - Move env back to being right after the MBR
Changes in v3:
 - fix spacing between asterix
 - remove verify=n as a default setting

Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE and fdt_addr
 - cleanup spacing in MMC env size

common
Signed-off-by: NDalon Westergreen <dwesterg@gmail.com>

Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add compatible strings for Intel Arria 10 SoCFPGA device.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Disable the OC test on MCVEVK as the old PHY version does not provide
this information. This fixes the USB OTG operation.
Signed-off-by: NMarek Vasut <marex@denx.de>

Add default DFU altinfo for eMMC.
Signed-off-by: NMarek Vasut <marex@denx.de>

There is no point in having such gargantuan buffer, it only requires
huge malloc area. Reduce the DFU buffer size.
Signed-off-by: NMarek Vasut <marex@denx.de>

The board is now manufactured by Aries Embedded GmbH , rename it.
Signed-off-by: NMarek Vasut <marex@denx.de>

Commit ce62e57f ("ARM: boot0 hook: remove macro, include whole
header file") miss out cleaning macro in this header file, and this
has broken implementation of a boot header capability in socfpga
SPL. Remove the macro in this file, and recovering it back
to proper functioning.

Fixes: ce62e57f ("ARM: boot0 hook: remove macro, include whole
header file")
Signed-off-by: NChee, Tien Fong <tien.fong.chee@intel.com>

With the port C enabled, we can read the GPI input state of:
* the DIP switches (USER_DIPSW_HPS[3:0]/HPS_GPI[7:4])
* the push buttons (USER_PB_HPS[3:0]/HPS_GPI[11:8])
Signed-off-by: NGeorges Savoundararadj <savoundg@gmail.com>
Signed-off by: Sid-Ali Teir <git.syedelec@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Marek Vasut <marex@denx.de>