- 09 5月, 2019 11 次提交
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由 Chen-Yu Tsai 提交于
The Cubietruck Plus has an RTL8211E PHY connected to the EMAC using RGMII. The PHY is powered by DLDO4 @ 3.3V, while the I/O pins are powered by DLDO3 @ 2.5V. This patch enables the EMAC and Realtek PHY drivers in the defconfig. The device tree file already has the EMAC enabled. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jonas Smedegaard 提交于
Olimex A64-Teres-I board is a mainboard (the only one so far) for Olimex Teres-I DIY laptop kit. Key features: - Allwinner A64 Cortex-A53 - Mali-400MP2 GPU - AXP803 PMIC - 2GB DDR3 RAM - MicroSD Slot - 16GB eMMC Flash - eDP LCD display - HDMI - USB Host - Battery management - 5V DC power supply - Certified Open Source Hardware (OSHW) Works: - i2C - MMC/SD - PWM backlight Known broken: - Internal keyboard (seems to be because the keyboard firmware loads a bootloader first, and then disconnects bootloader and connect real keyboard). External ones connected to the USB port work fine. This patch enables support for the A64-Teres-I board to u-boot, including enabling screen backlight (lacking from Linux device-tree). Linux commit details about the sun50i-a64-teres-i.dts sync: "arm64: dts: allwinner: a64: Rename uart0_pins_a label to uart0_pb_pins" (sha1: d91ebb95b96c8840932dc3a10c9f243712555467) Cosmetic warnings regarding whitespace and placement of SPDX notice for dts file was ignored. config and .dtsi file are adapted from pinebook files. Tested-by: NJonas Smedegaard <dr@jones.dk> Signed-off-by: NJonas Smedegaard <dr@jones.dk> Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com> [jagan: move board entry in MAINTAINERS file at proper position] Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Jagan Teki 提交于
Add sample dm reset test for reset_get_by_index and reset_get_by_index_nodev functionality code. Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Jagan Teki 提交于
Getting a RESET by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process RESET operation for child without udevice but with ofnode. So add reset_get_by_index_nodev() and move the common code in reset_get_by_index_tail() to use for reset_get_by_index() Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Jagan Teki 提交于
Add sample dm clk test for clk_get_by_index and clk_get_by_index_nodev functionality code. Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Jagan Teki 提交于
clk_get_by_index_tail() now handle common clk get by index code so use it from clk_get_by_indexed_prop(). Cc: Stephen Warren <swarren@nvidia.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Getting a CLK by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process CLK operation for child without udevice but with ofnode. So add clk_get_by_index_nodev() and move the common code in clk_get_by_index_tail() to use for clk_get_by_index() Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Jagan Teki 提交于
Like clk_get_by_index, there is requirement for clk_get_by_index_nodev. In this case to make common code functionalities for dev and nodev, clk_get_by_index is trying to get the index of clock by passing ofnode instead of actual dev like current gpio uclass does. In these scenarios with current order of include files the serial_sifive driver is unable to find CONFIG_ENV_SIZE. In file included from arch/riscv/include/asm/u-boot.h:23:0, from include/dm/of.h:10, from include/dm/ofnode.h:12, from include/clk.h:11, from drivers/serial/serial_sifive.c:6: include/environment.h:145:19: error: 'CONFIG_ENV_SIZE' undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'? #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) So, fix consists of changing the order of include files in serial_sifive.c to include first common.h file. Cc: Anup Patel <Anup.Patel@wdc.com> Cc: Rick Chen <rick@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Like clk_get_by_index, there is requirement for clk_get_by_index_nodev. In this case to make common code functionalities for dev and nodev, clk_get_by_index is trying to get the index of clock by passing ofnode instead of actual dev like current gpio uclass does. In these scenarios with current order of include files the fu540-prci driver is unable to find CONFIG_ENV_SIZE. In file included from arch/riscv/include/asm/u-boot.h:23:0, from include/dm/of.h:10, from include/dm/ofnode.h:12, from include/clk.h:11, from include/clk-uclass.h:13, from drivers/clk/sifive/fu540-prci.c:32: include/environment.h:145:19: error: 'CONFIG_ENV_SIZE' undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'? #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) So, fix consists of changing the order of include files in fu540-prci.c to include first common.h file. Cc: Anup Patel <Anup.Patel@wdc.com> Cc: Rick Chen <rick@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Like clk_get_by_index, there is requirement for clk_get_by_index_nodev. In this case to make common code functionalities for dev and nodev, clk_get_by_index is trying to get the index of clock by passing ofnode instead of actual dev like current gpio uclass does. In these scenarios with current order of include files the atcspi200_spi driver is unable to find CONFIG_ENV_SIZE. In file included from arch/nds32/include/asm/u-boot.h:24, from include/dm/of.h:10, from include/dm/ofnode.h:12, from include/clk.h:11, from drivers/spi/atcspi200_spi.c:9: include/environment.h:145:19: error: 'CONFIG_ENV_SIZE' undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'? #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) So, fix consists of changing the order of include files in atcspi200_spi.c to include first common.h file. Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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- 19 4月, 2019 3 次提交
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由 Ondrej Jirman 提交于
Fixes a compilation failure with disabled PXE or DHCP command when using sunxi platform. Signed-off-by: NOndřej Jirman <megous@megous.com> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Clément Péron 提交于
Beelink GS1 is an Allwinner H6 based TV box, which support: - Allwinner H6 Quad-core 64-bit ARM Cortex-A53 - GPU Mali-T720 - 2GB LPDDR3 RAM - 16GB eMMC - AXP805 PMIC - 1Gbps GMAC via RTL8211E - USB 2.0 and 3.0 Host - HDMI port - S/PDIF port - 5V/2A DC power supply - Wi-Fi/BT via Fn-Link 6222B-SRB (RTL8222BS) Linux commit details about the sun50i-h6-beelink-gs1.dts sync: "arm64: dts: allwinner: h6: Introduce Beelink GS1 board" (sha1: 089bee8dd119ba084dee6b17a2e1a53df4f30193) Signed-off-by: NClément Péron <peron.clem@gmail.com> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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git://git.denx.de/u-boot-arc由 Tom Rini 提交于
In this small series we migrate ARC boards to DM_MMC so we're hopefully are good now and our boards will be kept in U-Boot for some more time :)
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- 18 4月, 2019 3 次提交
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由 Eugeniy Paltsev 提交于
Signed-off-by: NEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
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由 Eugeniy Paltsev 提交于
Signed-off-by: NEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
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由 Eugeniy Paltsev 提交于
Add the DM_MMC-compatible DesignWare MMC driver support for Synopsys ARC devboards. It is created to switch ARC devboards to use DM_MMC. It required information such as clocks (Bus Interface Unit clock, Card Interface Unit clock) and SDIO bus width. Signed-off-by: NEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
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- 17 4月, 2019 17 次提交
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git://git.denx.de/u-boot-spi由 Tom Rini 提交于
- drop non-DM code from ti_qspi - support spi-mem for ti_qspi
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由 Uri Mashiach 提交于
U-Boot support for the CL-SOM-AM57x module is no longer required. Signed-off-by: NUri Mashiach <uri.mashiach@compulab.co.il>
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git://git.denx.de/u-boot-sunxi由 Tom Rini 提交于
- Convert DM_MMC and DM_SCSI - A20, R40, H6 Linux dts(i) sync - CLK, RESET support for sunxi, sun8_emac net drivers
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git://git.denx.de/u-boot-microblaze由 Tom Rini 提交于
Xilinx/FPGA changes for v2019.07 fpga: - Add support for external data in FIT - Extend testing for external data case - Inform user about a need to run post config on Zynq arm: - Tune zynq command functions - Fix internal variable setting arm64: - Add support for zc39dr decoding - Disable WDT for zcu100 - Small changes in reset_reason() - Some DT changes (spi) - Tune qspi-mini configuration - Remove useless eeprom setting - Fix two sdhci boot case spi: - Fix tap delay programming clk: - Enable i2c in SPL net: - Fix gem phydev handling - Remove phy detection code from gem driver general: - Correct EXT_DTB usage for MULTI_DTB_FIT configuration
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git://git.denx.de/u-boot-uniphier由 Tom Rini 提交于
UniPhier SoC updates for v2019.07 - Sync DT with Linux 5.1-rc4 - Enable CONFIG_SUPPORT_EMMC_RPMB for uniphier_v8_defconfig
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由 Vignesh Raghavendra 提交于
Convert driver to use spi-mem ops in order to support accelerated MMIO flash interface in generic way and for better performance. Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Acked-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Vignesh Raghavendra 提交于
Now that all boards using TI QSPI have moved to DM and DT, drop non DM code completely. Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> [jagan: update MIGRATION.txt, rebase config_whitelist.txt] Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
It seems like the Allwinner SATA driver is already quite capable of using the driver model, so we can force this on all boards and can remove support for a non-DM_SCSI build. This removes the warning about boards with SATA ports not being DM_SCSI compliant. It also takes the opportunity to move the driver out of the board/sunxi directory to join its siblings in drivers/ata, and to make it a proper Kconfig citizen. The board defconfigs stay untouched. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NJagan Teki <jagan@openedev.com> [jagan: select DM_SCSI separately] Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
- Enable DM_MMC if MMC defined - Enable DM_SCSI if SCSI defined globally through Allwinner platform, the effected SoC families and boards will make use of MMC and SCSI subsystems in driver-model. Tested DM_MMC in one board from A64, H6, H5, H3, R40, A83T, A20, A10 SoCs. Tested-by: Pablo Sebastián Greco <pgreco@centosproject.org> # BPI-M2-Ultra Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Enable ahci node for BPI-M2-Berry, this would require since we have DM_SCSI enabled on the respective SoC. Unable to sync the same node from Linux, since the similar change is still in Linux ML. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Enable ahci node for a20-wits-pro-a20-dkt, this would require since we have DM_SCSI enabled on the respective SoC. Right now, ahci enabled in -u-boot.dtsi and will remove once same supported by Linux. Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Enable ahci node for sun7i-a20-m5.dts, this would require since we have DM_SCSI enabled on the respective SoC. No need to send patch to Linux for this change, since this dts is U-Boot specific. Cc: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add sata compatible for R40. Cc: Pablo Sebastián Greco <pgreco@centosproject.org> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Sync sun7i-a20 dts(i) files from Linux 5.1-rc2 Linux commit details about the sun7i-a20* sync: "ARM: dts: sun7i: bananapi: Add GPIO banks regulators" (sha1: 09c6572290f018d73ec2e812e28bada34d41815f) Here are U-Boot specific dts changes. - s/uart0_pins_a/uart0_pb_pins for sun7i-a20-ainol-aw1.dts sun7i-a20-m5.dts sun7i-a20-primo73.dts sun7i-a20-yones-toptech-bd1078.dts sunxi-itead-core-common.dtsi - s/gmac_pins_mii_a/gmac_rgmii_pins for sun7i-a20-m5.dts - drop i2c0, i2c1 pins from sunxi-itead-core-common.dtsi - drop mmc0 pins from sun7i-a20-primo73.dts Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Sync sun8i-r40 dts(i) files from Linux 5.1-rc2 Linux commit details about the sun8i-r40* sync: "ARM: dts: sun8i: r40: bananapi-m2-ultra: Add Bluetooth device node" (sha1: 1e5f1db4ccd8348a21da55bff82f4263000879ef) Linux commit details about the sun8i-v40* sync: "ARM: dts: sunxi: Fix I2C bus warnings" (sha1: 0729b4af5753b65aa031f58c435da53dbbf56d19) Cc: Pablo Sebastián Greco <pgreco@centosproject.org> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Masahiro Yamada 提交于
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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- 16 4月, 2019 6 次提交
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由 Jagan Teki 提交于
Since Ethernet clock and reset is now handling via CLK and RESET frameworks via driver API's remove explicit ccm writes. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Jagan Teki 提交于
Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add CLk support for sunxi_emac to enable AHB_EMAC clock via CLK framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Jagan Teki 提交于
GMAC reset reg offset added by below commit seems to assume it as EMAC but R40 indeed using GMAC. "clk: sunxi: Implement EMAC, GMAC clocks, resets" (sha1: 68620c96) So, fix by updating the reg offset for RST_BUS_GMAC. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Luca Ceresoli 提交于
A missing CONFIG_ prefix while checking for this Kconfig variable makes the check always fail. Fix it. While there also switch from the '#if defined' form to the '#ifdef' form as the other checks in this function. Fixes: 35e2b923 ("arm64: zynqmp: Fix logic around CONFIG_ZYNQ_SDHCI") Signed-off-by: NLuca Ceresoli <luca@lucaceresoli.net> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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