Merge tag 'xilinx-for-v2019.07' of git://git.denx.de/u-boot-microblaze

Xilinx/FPGA changes for v2019.07

fpga:
- Add support for external data in FIT
- Extend testing for external data case
- Inform user about a need to run post config on Zynq

arm:
- Tune zynq command functions
- Fix internal variable setting

arm64:
- Add support for zc39dr decoding
- Disable WDT for zcu100
- Small changes in reset_reason()
- Some DT changes (spi)
- Tune qspi-mini configuration
- Remove useless eeprom setting
- Fix two sdhci boot case

spi:
- Fix tap delay programming

clk:
- Enable i2c in SPL

net:
- Fix gem phydev handling
- Remove phy detection code from gem driver

general:
- Correct EXT_DTB usage for MULTI_DTB_FIT configuration

Makefile

@@ -1052,8 +1052,13 @@ MKIMAGEFLAGS_fit-dtb.blob = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
 	-a 0 -e 0 -E \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -d /dev/null
 
+ifneq ($(EXT_DTB),)
+u-boot-fit-dtb.bin: u-boot-nodtb.bin $(EXT_DTB)
+		$(call if_changed,cat)
+else
 u-boot-fit-dtb.bin: u-boot-nodtb.bin $(FINAL_DTB_CONTAINER)
 	$(call if_changed,cat)
+endif
 
 u-boot.bin: u-boot-fit-dtb.bin FORCE
 	$(call if_changed,copy)

arch/arm/dts/zynqmp-mini-qspi.dts

@@ -63,8 +63,8 @@
 
 &qspi {
 	status = "okay";
-	flash@0 {
-		compatible = "n25q512a11";
+	flash0: flash@0 {
+		compatible = "n25q512a11", "spi-flash";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;

arch/arm/mach-zynqmp/spl.c

@@ -27,6 +27,7 @@ void board_init_f(ulong dummy)
 	/* Delay is required for clocks to be propagated */
 	udelay(1000000);
 
+	debug("Clearing BSS 0x%p - 0x%p\n", __bss_start, __bss_end);
 	/* Clear the BSS */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
@@ -85,7 +86,7 @@ u32 spl_boot_device(void)
 	case SD_MODE1:
 	case SD1_LSHFT_MODE: /* not working on silicon v1 */
 /* if both controllers enabled, then these two are the second controller */
-#if defined(SPL_ZYNQMP_TWO_SDHCI)
+#ifdef CONFIG_SPL_ZYNQMP_TWO_SDHCI
 		return BOOT_DEVICE_MMC2;
 /* else, fall through, the one SDHCI controller that is enabled is number 1 */
 #endif

board/xilinx/zynq/cmds.c

@@ -414,9 +414,13 @@ static int do_zynq_rsa(cmd_tbl_t *cmdtp, int flag, int argc,
 	u32 src_ptr;
 	char *endp;
 
+	if (argc != cmdtp->maxargs)
+		return CMD_RET_FAILURE;
+
 	src_ptr = simple_strtoul(argv[2], &endp, 16);
 	if (*argv[2] == 0 || *endp != 0)
 		return CMD_RET_USAGE;
+
 	if (zynq_verify_image(src_ptr))
 		return CMD_RET_FAILURE;
 
@@ -432,6 +436,9 @@ static int zynq_decrypt_image(cmd_tbl_t *cmdtp, int flag, int argc,
 	u32 srcaddr, srclen, dstaddr, dstlen;
 	int status;
 
+	if (argc < 5 && argc > cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
 	srcaddr = simple_strtoul(argv[2], &endp, 16);
 	if (*argv[2] == 0 || *endp != 0)
 		return CMD_RET_USAGE;
@@ -485,7 +492,7 @@ static int do_zynq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		return CMD_RET_USAGE;
 	zynq_cmd = find_cmd_tbl(argv[1], zynq_commands,
 				ARRAY_SIZE(zynq_commands));
-	if (!zynq_cmd || argc != zynq_cmd->maxargs)
+	if (!zynq_cmd)
 		return CMD_RET_USAGE;
 
 	ret = zynq_cmd->cmd(zynq_cmd, flag, argc, argv);

board/xilinx/zynqmp/zynqmp.c

@@ -170,6 +170,10 @@ static const struct {
 		.id = 0x62,
 		.name = "29dr",
 	},
+	{
+		.id = 0x66,
+		.name = "39dr",
+	},
 };
 #endif
 
@@ -482,18 +486,20 @@ static const struct {
 	{}
 };
 
-static u32 reset_reason(void)
+static int reset_reason(void)
 {
-	u32 ret;
-	int i;
+	u32 reg;
+	int i, ret;
 	const char *reason = NULL;
 
-	ret = readl(&crlapb_base->reset_reason);
+	ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
+	if (ret)
+		return -EINVAL;
 
 	puts("Reset reason:\t");
 
 	for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
-		if (ret & reset_reasons[i].bit) {
+		if (reg & reset_reasons[i].bit) {
 			reason = reset_reasons[i].name;
 			printf("%s ", reset_reasons[i].name);
 			break;
@@ -504,7 +510,9 @@ static u32 reset_reason(void)
 
 	env_set("reset_reason", reason);
 
-	writel(~0, &crlapb_base->reset_reason);
+	ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
+	if (ret)
+		return -EINVAL;
 
 	return ret;
 }

cmd/fpga.c

@@ -343,9 +343,9 @@ static int do_fpga_loadmk(cmd_tbl_t *cmdtp, int flag, int argc,
 			return CMD_RET_FAILURE;
 		}
 
-		/* get fpga subimage data address and length */
-		if (fit_image_get_data(fit_hdr, noffset, &fit_data,
-				       &data_size)) {
+		/* get fpga subimage/external data address and length */
+		if (fit_image_get_data_and_size(fit_hdr, noffset,
+					       &fit_data, &data_size)) {
 			puts("Fpga subimage data not found\n");
 			return CMD_RET_FAILURE;
 		}

configs/xilinx_zynqmp_mini_qspi_defconfig

@@ -6,8 +6,10 @@ CONFIG_ENV_SIZE=0x80
 CONFIG_SPL=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 CONFIG_ZYNQMP_NO_DDR=y
+# CONFIG_PSCI_RESET is not set
 # CONFIG_CMD_ZYNQMP is not set
 CONFIG_NR_DRAM_BANKS=1
+# CONFIG_EXPERT is not set
 # CONFIG_IMAGE_FORMAT_LEGACY is not set
 # CONFIG_BOARD_LATE_INIT is not set
 # CONFIG_DISPLAY_CPUINFO is not set

configs/xilinx_zynqmp_zcu100_revC_defconfig

@@ -85,8 +85,6 @@ CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
-CONFIG_WDT=y
-CONFIG_WDT_CDNS=y
 CONFIG_SPL_GZIP=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

drivers/clk/clk_zynq.c

@@ -434,6 +434,8 @@ static ulong zynq_clk_get_rate(struct clk *clk)
 	case lqspi_clk ... pcap_clk:
 	case sdio0_clk ... spi1_clk:
 		return zynq_clk_get_peripheral_rate(priv, id, 0);
+	case i2c0_aper_clk ... i2c1_aper_clk:
+		return zynq_clk_get_cpu_rate(priv, cpu_1x_clk);
 	default:
 		return -ENXIO;
 	}

drivers/fpga/zynqpl.c

@@ -408,6 +408,8 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
 	if (bstype != BIT_PARTIAL)
 		zynq_slcr_devcfg_enable();
 
+	puts("INFO:post config was not run, please run manually if needed\n");
+
 	return FPGA_SUCCESS;
 }
 
@@ -421,7 +423,8 @@ static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
 	loff_t blocksize, actread;
 	loff_t pos = 0;
 	int fstype;
-	char *interface, *dev_part, *filename;
+	char *interface, *dev_part;
+	const char *filename;
 
 	blocksize = fsinfo->blocksize;
 	interface = fsinfo->interface;

drivers/net/zynq_gem.c

@@ -261,45 +261,6 @@ static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
 			    ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
 }
 
-static int phy_detection(struct udevice *dev)
-{
-	int i;
-	u16 phyreg = 0;
-	struct zynq_gem_priv *priv = dev->priv;
-
-	if (priv->phyaddr != -1) {
-		phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
-		if ((phyreg != 0xFFFF) &&
-		    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
-			/* Found a valid PHY address */
-			debug("Default phy address %d is valid\n",
-			      priv->phyaddr);
-			return 0;
-		} else {
-			debug("PHY address is not setup correctly %d\n",
-			      priv->phyaddr);
-			priv->phyaddr = -1;
-		}
-	}
-
-	debug("detecting phy address\n");
-	if (priv->phyaddr == -1) {
-		/* detect the PHY address */
-		for (i = 31; i >= 0; i--) {
-			phyread(priv, i, PHY_DETECT_REG, &phyreg);
-			if ((phyreg != 0xFFFF) &&
-			    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
-				/* Found a valid PHY address */
-				priv->phyaddr = i;
-				debug("Found valid phy address, %d\n", i);
-				return 0;
-			}
-		}
-	}
-	printf("PHY is not detected\n");
-	return -1;
-}
-
 static int zynq_gem_setup_mac(struct udevice *dev)
 {
 	u32 i, macaddrlow, macaddrhigh;
@@ -345,28 +306,20 @@ static int zynq_phy_init(struct udevice *dev)
 	/* Enable only MDIO bus */
 	writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
 
-	if ((priv->interface != PHY_INTERFACE_MODE_SGMII) &&
-	    (priv->interface != PHY_INTERFACE_MODE_GMII)) {
-		ret = phy_detection(dev);
-		if (ret) {
-			printf("GEM PHY init failed\n");
-			return ret;
-		}
-	}
-
 	priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
 				   priv->interface);
 	if (!priv->phydev)
 		return -ENODEV;
 
-	priv->phydev->supported &= supported | ADVERTISED_Pause |
-				  ADVERTISED_Asym_Pause;
 	if (priv->max_speed) {
 		ret = phy_set_supported(priv->phydev, priv->max_speed);
 		if (ret)
 			return ret;
 	}
 
+	priv->phydev->supported &= supported | ADVERTISED_Pause |
+				  ADVERTISED_Asym_Pause;
+
 	priv->phydev->advertising = priv->phydev->supported;
 	priv->phydev->node = priv->phy_of_node;
 

drivers/spi/zynqmp_gqspi.c

@@ -267,7 +267,7 @@ void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
 		zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 		tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 				TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
-	} else if (reqhz < GQSPI_FREQ_100MHZ) {
+	} else if (reqhz <= GQSPI_FREQ_100MHZ) {
 		zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 		tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 				TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
@@ -277,7 +277,7 @@ void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
 		datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
 				| (GQSPI_DATA_DLY_ADJ_VALUE <<
 					GQSPI_DATA_DLY_ADJ_SHIFT));
-	} else if (reqhz < GQSPI_FREQ_150MHZ) {
+	} else if (reqhz <= GQSPI_FREQ_150MHZ) {
 		lpbkdlyadj = readl(&regs->lpbkdly);
 		lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) |
 				GQSPI_LPBK_DLY_ADJ_DLY_0);

include/configs/xilinx_zynqmp.h

@@ -108,15 +108,6 @@
 # define PHY_ANEG_TIMEOUT       20000
 #endif
 
-/* EEPROM */
-#ifdef CONFIG_ZYNQMP_EEPROM
-# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
-# define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
-# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
-# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
-# define CONFIG_SYS_EEPROM_SIZE			(64 * 1024)
-#endif
-
 #define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
 
 #define CONFIG_CLOCKS

include/configs/zynq-common.h

@@ -69,7 +69,7 @@
 # define CONFIG_THOR_RESET_OFF
 # define DFU_ALT_INFO_RAM \
 	"dfu_ram_info=" \
-	"set dfu_alt_info " \
+	"setenv dfu_alt_info " \
 	"${kernel_image} ram 0x3000000 0x500000\\\\;" \
 	"${devicetree_image} ram 0x2A00000 0x20000\\\\;" \
 	"${ramdisk_image} ram 0x2000000 0x600000\0" \
@@ -79,7 +79,7 @@
 # if defined(CONFIG_MMC_SDHCI_ZYNQ)
 #  define DFU_ALT_INFO_MMC \
 	"dfu_mmc_info=" \
-	"set dfu_alt_info " \
+	"setenv dfu_alt_info " \
 	"${kernel_image} fat 0 1\\\\;" \
 	"${devicetree_image} fat 0 1\\\\;" \
 	"${ramdisk_image} fat 0 1\0" \
@@ -227,9 +227,9 @@
 				"env run importbootenv; " \
 			"fi; " \
 		"fi; \0" \
-	"sd_loadbootenv=set bootenv_dev mmc && " \
+	"sd_loadbootenv=setenv bootenv_dev mmc && " \
 			"run setbootenv \0" \
-	"usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv \0" \
+	"usb_loadbootenv=setenv bootenv_dev usb && usb start && run setbootenv \0" \
 	"preboot=if test $modeboot = sdboot; then " \
 			"run sd_loadbootenv; " \
 			"echo Checking if uenvcmd is set ...; " \

include/fpga.h

@@ -41,7 +41,7 @@ typedef struct {                /* typedef fpga_desc */
 	unsigned int blocksize;
 	char *interface;
 	char *dev_part;
-	char *filename;
+	const char *filename;
 	int fstype;
 } fpga_fs_info;
 

test/py/tests/test_fpga.py

@@ -353,6 +353,19 @@ def test_fpga_loadmk_legacy_gz(u_boot_console):
     output = u_boot_console.run_command('fpga loadmk %x %x && echo %s' % (dev, addr, expected_text))
     assert expected_text in output
 
+@pytest.mark.buildconfigspec('cmd_fpga')
+@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
+@pytest.mark.buildconfigspec('fit')
+@pytest.mark.buildconfigspec('cmd_echo')
+def test_fpga_loadmk_fit_external(u_boot_console):
+    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_fit_external')
+
+    u_boot_console.run_command('imi %x' % (addr))
+
+    expected_text = 'FPGA loaded successfully'
+    output = u_boot_console.run_command('fpga loadmk %x %x:fpga && echo %s' % (dev, addr, expected_text))
+    assert expected_text in output
+
 @pytest.mark.buildconfigspec('cmd_fpga')
 @pytest.mark.buildconfigspec('cmd_fpga_loadmk')
 @pytest.mark.buildconfigspec('fit')