These files are used by both SPL and main U-Boot.
Also made minor changes to shared Tegra code to support
T30 differences.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h.
Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs
that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20'
'root' file.

All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK.
Signed-off-by: NTom Warren <twarren@nvidia.com>

Move files that are going to be common between T20 and T30 into 'tegra-common'
subdirs in AVP (arm720t), CPU (armv7), and shared (arch/arm/cpu/.) areas. Any
files that are left behind in '/tegra20' will be copied to '/tegra30' subdirs
and modified for that SoC. The 'common' files should need only minor changes.

Include files (arch/arm/include/asm/arch-tegra/tegra20) will be done in a
follow-on patch.

Builds fine w/MAKEALL -s tegra20. Checkpatch.pl is clean.
Signed-off-by: NTom Warren <twarren@nvidia.com>

Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate.
Convert tegra20_ source file and function names to tegra_, also.

Upcoming Tegra30 port will use common code/defines/names where possible.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>

Add SPL options to tegra20 config files and enable SPL build for
tegra20 boards.  Also remove redundant code from u-boot that is not
contained in SPL.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Tested-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Move warmboot_save_sdram_params() to later in the boot sequence.  This
code relies on devicetree to get the address of the memory controller
and with upcoming changes for SPL boot it gets called early in the
boot process when devicetree is not initialized yet.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Tested-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NTom Warren <twarren@nvidia.com>

In preparation for splitting out the armv4t code from tegra20, move
the tegra20 SoC code to arch/arm/cpu/tegra20-common.  This code will
be compiled armv4t for the arm7tdmi and armv7 for the cortex A9.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Tested-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NTom Warren <twarren@nvidia.com>

This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Tested-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Walk the BIT and BCT to find the ODMDATA word in the
CustomerData field and put it into Scratch20 reg for
use by kernel, etc.

Built all Tegra builds OK; Booted on Seaboard and saw
ODMDATA in PMC scratch20 was the same as the value in my
burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities
will have to specify the odmdata (nvflash --odmdata n) on
the command line or via a cfg file, or built in to their
BCT.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>

Correct this warning seen by Albert:

ap20.c:44:18: warning: array subscript is above array bounds

There is a subtle bug here which currently causes no errors, but might
in future if people use PCI or the 32KHz clock. So take the opportunity
to correct the logic now.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Save SDRAM parameters into the warmboot scratch registers
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NYen Lin <yelin@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

We want to know which type of chip we are running on - the Tegra
family has several SKUs. This can be determined by reading a
fuse register, so add this function to ap20.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

We want to include this from board code, so move the header into
an easily-accessible location.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Change this name to fit with the current convention in the Tegra
header file.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

The 4.2.2 gcc in the ELDK42 release doesn't like the direct SP
load using a constant in tegra2_start. Change it to use a load
thru another reg using mov sp, %0 : : "r"(CONST).

Tested on my Seaboard T20-A03, U-Boot loads and runs OK. Also
compiled all tegra2 builds with both gcc 4.2.2 and 4.4.1 OK.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>

The Tegra2 boot path is more complicated than it needs to be. Since we want
to move to building most of U-Boot with ARMv7 and only a small part with
ARMv4T (for AVP) it should be as simple as possible.

This makes tegra2_start() into a simple function which either does AVP
init or A9 init depending on which core is running it. Both cores now
following the same init path, beginning at _start, and the special Tegra2
boot path code is no longer required.

Only two files need to be built for ARMv4T, and this is handled in the
Tegra2 CPU Makefile.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

This adds most of the clock functions required by board and driver code:

-query and adjust peripheral clocks
-query and adjust PLLs
-reset and enable control

These functions are plumbed in as required.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NTom Warren <twarren@nvidia.com>

Rename CLOCK_PLL_ID to CLOCK_ID which takes account of the fact that the
code now deals with both PLL clocks and source clocks.

This also tidied up the assert() to match the one sent upstream, and fixes
an error in the PWM id.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NTom Warren <twarren@nvidia.com>

Signed-off-by: NSimon Glass <sjg@chromium.org>

This adds functions to enable/disable clocks and reset to on-chip peripherals.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NTom Warren <twarren@nvidia.com>

Signed-off-by: NTom Warren <twarren@nvidia.com>