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  1. 17 1月, 2013 5 次提交
  3. 15 1月, 2013 1 次提交
  5. 13 1月, 2013 1 次提交
  7. 12 1月, 2013 1 次提交
  9. 11 1月, 2013 10 次提交
    • J
      Exynos: clock: add CLK_DIV_FSYS3 at set_mmc_clk · 5374d386
      由 Jaehoon Chung 提交于 
      Mobile storage is used the CLK_DIV_FSYS3 value.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Nkyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
      5374d386
    • J
      Exynos: clock: support get_mmc_clk for exynos · c39e969e
      由 Jaehoon Chung 提交于 
      To get exactly clock value for mmc, support the get_mmc_clk() like
set_mmc_clk().
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
      c39e969e
    • T
      arm: Tabify code for MMC initialization · 80e40950
      由 Taylor Hutt 提交于 
      The two modified lines were indented with spaces.
They are now indented with tabs.
Signed-off-by: NTaylor Hutt <thutt@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>
      80e40950
    • S
      arm: Move bootstage record for board_init_f() to after arch_cpu_init() · 2f8d8d6b
      由 Simon Glass 提交于 
      The timer may be inited in arch_cpu_init() so it is not safe to make a
bootstage mark before this is called. Arrange the code to fix this.

Note: The question was raised as to why we don't keep all archs in sync.
PowerPC doesn't have specific bootstage markers at present (although it
does use boot progress). I hope that the generic board series will solve
this problem in general, but in the meantime this is a real problem, and
only in ARM.

We now get a correct time for board_init_f:

Timer summary in microseconds:
       Mark    Elapsed  Stage
          0          0  reset
    100,000    100,000  spl_start
    848,530    748,530  board_init_f
    907,301     58,771  board_init_r
    910,478      3,177  board_init
Signed-off-by: NSimon Glass <sjg@chromium.org>
      2f8d8d6b
    • T
      arm: Make interrupts.o and reset.o in libarm also appear in SPL · fe34f8dc
      由 Tom Wai-Hong Tam 提交于 
      SPL u-boot may call do_reset() which depends on interrupts.o and reset.o.
So make them also appear in SPL.
Signed-off-by: NTom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>
      fe34f8dc
    • S
      arm: Add CONFIG_DISPLAY_BOARDINFO_LATE to display board info on LCD · e2e3e2b1
      由 Simon Glass 提交于 
      This option displays board info after stdio is running, so that it will
appear on the LCD. If it is displayed earlier, the board info will appear
on the serial console but not on the LCD.

Here follows a blow-by-blow description.

1a. Without CONFIG_DISPLAY_BOARDINFO_LATE, on serial:

U-Boot 2011.12-02550-g037e1c5-dirty (Nov 15 2012 - 14:29:42) for SMDK5250

CPU:   S5PC520 @ 1700MHz

Board: Google Snow, rev 0
I2C:   ready
DRAM:  2 GiB Elpida DDR3 @ 800MHz
MMC:   S5P MSHC0: 0, S5P MSHC1: 1
SF: Detected W25Q32 with page size 4 KiB, total 4 MiB
*** Warning - bad CRC, using default environment

In:    mkbp-keyb
Out:   lcd
Err:   lcd
Net:   No ethernet found.
Hit any key to stop autoboot:  0
SMDK5250 #

1b. Without CONFIG_DISPLAY_BOARDINFO_LATE, on LCD (note machine info
is missing):

In:    mkbp-keyb
Out:   lcd
Err:   lcd
Net:   No ethernet found.
Hit any key to stop autoboot:  0
SMDK5250 #

2a. With CONFIG_DISPLAY_BOARDINFO_LATE, on serial:

U-Boot 2011.12-02550-g037e1c5 (Nov 15 2012 - 14:27:40) for SMDK5250

CPU:   S5PC520 @ 1700MHz
I2C:   ready
DRAM:  2 GiB Elpida DDR3 @ 800MHz
MMC:   S5P MSHC0: 0, S5P MSHC1: 1
SF: Detected W25Q32 with page size 4 KiB, total 4 MiB
*** Warning - bad CRC, using default environment

Model: Google Snow
In:    mkbp-keyb
Out:   lcd
Err:   lcd
Net:   No ethernet found.
Hit any key to stop autoboot:  0
SMDK5250 #

2b. With CONFIG_DISPLAY_BOARDINFO_LATE, on LCD (note machine info is present):

Model: Google Snow
In:    mkbp-keyb
Out:   lcd
Err:   lcd
Net:   No ethernet found.
Hit any key to stop autoboot:  0
SMDK5250 #

Since the LCD is all that a typical user sees, it is useful to display
the model there.

We may be able to rearrange things some other way one day, but at
present this seems like a convenient way of getting the required
behaviour.
Signed-off-by: NSimon Glass <sjg@chromium.org>
      e2e3e2b1
    • S
      arm: Add CONFIG_DELAY_ENVIRONMENT to delay environment loading · 06fd8538
      由 Simon Glass 提交于 
      This option delays loading of the environment until later, so that only the
default environment will be available to U-Boot.

This can address the security risk of untrusted data being used during boot.

Any time you load untrusted data you expose yourself to a bug in the
code. The attacker gets to choose the data so can sometimes carefully
craft it to exploit a bug. We try to avoid touching user-controlled
data during a verified boot unless strictly necessary. Since the
default environment is good enough in this case (or you would just
change it), this gets around the problem by just not loading the
environment.

When CONFIG_DELAY_ENVIRONMENT is defined, it is convenient to have a
run-time way of enabling loading of the environment. Add this to the
fdt as /config/delay-environment.

Note: This patch depends on http://patchwork.ozlabs.org/patch/194342/Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
      06fd8538
    • S
      arm: Move fdt check earlier so that board_early_init_f() can use it · eae78c34
      由 Simon Glass 提交于 
      We want to use the fdt inside board_early_init_f(), so check for its
presence earlier in the pre-reloc init sequence.

So far ARM and microblaze are the only only ones that use
CONFIG_OF_CONTROL. Microblaze does not have the same init loop, and in
particular does not have the board_early_init_f() call. So a patch for
microblaze would have no meaning.
Signed-off-by: NSimon Glass <sjg@chromium.org>
      eae78c34
    • G
      arm: Keep track of the tlb size as well as its location · 724cdffc
      由 Gabe Black 提交于 
      It may be necessary to know where the TLB area ends as well as where it
starts. This allows board code to complete a secure memory erase without
destroying the page tables.
Signed-off-by: NGabe Black <gabeblack@google.com>
Signed-off-by: NSimon Glass <sjg@chromium.org>
      724cdffc
    • A
      arm: move flush_dcache_all() to just before disable cache · 44df5e8d
      由 Arun Mankuzhi 提交于 
      In Cortex-A15 architecture, when we run cache invalidate
the cache clean operation executes automatically.
So if there are any dirty cache lines before disabling the L2 cache
these will be synchronized with the main memory when
invalidate_dcache_all() runs in the last part of U-boot

The two functions after flush_dcache_all is using the stack. So this
data will be on the cache. After disable when invalidate is called the
data will be flushed from cache to memory. This corrupts the stack in
invalida_dcache_all. So this change is required to avoid the u-boot
hang.

So flush has to be done just before clearing CR_C bit
Signed-off-by: NArun Mankuzhi <arun.m@samsung.com>
Signed-off-by: NSimon Glass <sjg@chromium.org>
      44df5e8d
  11. 10 1月, 2013 4 次提交
  13. 09 1月, 2013 4 次提交
  15. 08 1月, 2013 6 次提交
  17. 26 12月, 2012 6 次提交
  19. 20 12月, 2012 1 次提交
  21. 14 12月, 2012 1 次提交