EXYNOS5: Change parent clock of FIMD to MPLL

With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to MPLL resolves this issue.
Signed-off-by: NAjay Kumar <ajaykumar.rs@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Acked-by: NDonghwa Lee <dh09.lee@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

arch/arm/cpu/armv7/exynos/clock.c

@@ -741,7 +741,7 @@ void exynos5_set_lcd_clk(void)
 	 */
 	cfg = readl(&clk->src_disp1_0);
 	cfg &= ~(0xf);
-	cfg |= 0x8;
+	cfg |= 0x6;
 	writel(cfg, &clk->src_disp1_0);
 
 	/*